DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 379

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.1
TDPCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to
CKS0 in TDPCR1. When CKS2 to CKS0 are set to B'111, the external clock is selected. Rising or
falling edge is selected by CKSEG in TDPCSR.
When TDPCNT overflows (H'FFFF changes to H'0000), the OVF flag in TDPCSR is set to 1. In
timer mode, TDPCNT is initialized to H'0000 when the CST bit in TDPCR1 is cleared. In cycle
measurement mode, TDPCNT is cleared when the first edge (the edge selected by the IEDG bit in
TDPCR1) of the measurement period (equal to one input waveform period) is detected.
In timer mode, TDPCNT is always writable. In cycle measurement mode, TDPCNT cannot be
modified. TDPCNT must always be accessed in 16-bit units and cannot be accessed in 8-bit units.
TDPCNT is initialized to H'0000.
Channel
Channel 2
TDP Timer Counter (TDPCNT)
Register Name
TDP timer counter_2
TDP pulse width upper limit
register_2
TDP pulse width lower limit register_2 TDPWDMN_2 R/W
TDP cycle upper limit register_2
TDP cycle lower limit register_2
TDP input capture register_2
TDP input capture buffer register_2
TDP status register_2
TDP control register 1_2
TDP control register 2_2
TDP interrupt enable register_2
Section 12 16-Bit Duty Period Measurement Timer (TDP)
TDPPDMN_2 R/W
Abbreviation R/W
TDPCNT_2
TDPWDMX_2 R/W
TDPPDMX_2 R/W
TDPICR_2
TDPICRF_2
TDPCSR_2
TDPCR1_2
TDPCR2_2
TDPIER_2
Rev. 3.00 Sep. 28, 2009 Page 333 of 910
R/W
R
R
R/W
R/W
R/W
R/W
Initial
Value
H'0000 H'FB80 16
H'FFFF H'FB82 16
H'0000 H'FB84 16
H'FFFF H'FB86 16
H'0000 H'FB90 16
H'0000 H'FB88 16
H'0000 H'FB8A 16
H'00
H'00
H'00
H'00
Address
H'FB8C 8
H'FB8D 8
H'FB8F 8
H'FB8E 8
REJ09B0350-0300
Data
Bus
Width