DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 128

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Exception Handling
4.6
The exception handling by the illegal instruction starts when an undefined code is executed. The
exception handling by the illegal instruction is always executable in the program execution state.
The exception handling operates as follows:
1. The contents of the PC and CCR are saved in the stack.
2. The interrupt mask bit is updated.
3. An exception handling vector table address corresponding to the occurred exception is
Table 4.5 shows the state of CCR after execution of illegal instruction exception handling.
Table 4.5
Interrupt Control Mode
0
1
Illegal instruction code is not detected for fields that do not affect the definition of the instruction,
such as an effective address extension (EA) and register fields. In addition, the instruction code of
instructions consisting of multiple words are detected individually and are not detected as
combinations of instruction codes.
Do not execute instruction codes that are not defined. The contents of general registers are not
guaranteed after the execution of an undefined instruction code or exception handling by the
illegal instruction. The value of the stack pointer at the time of exception handling by the illegal
instruction and the saved contents of the PC are also not guaranteed.
Rev. 3.00 Sep. 28, 2009 Page 82 of 910
REJ09B0350-0300
generated, the start address of the exception service routine is loaded from the vector table to
the PC, and program execution starts from that address.
Exception Handling by Illegal Instruction
Status of CCR after Illegal Instruction Exception Handling
I
Set to 1
Set to 1
UI
Retains the previous value
Set to 1
CCR