DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 808

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 23 Clock Pulse Generator
Table 23.3 External Clock Input Conditions
The oscillator and duty correction circuit can adjust the waveform of the external clock input that
is input from the EXTAL pin.
When a specified clock signal is input to the EXTAL pin, internal clock signal output is
determined after the external clock output stabilization delay time (t
signal output is not determined during the t
maintain the reset state. Table 23.4 shows the external clock output stabilization delay time. Figure
23.6 shows the timing of the external clock output stabilization delay time.
Rev. 3.00 Sep. 28, 2009 Page 762 of 910
REJ09B0350-0300
Item
External clock input pulse
width low level
External clock input pulse
width high level
External clock rising time
External clock falling time
Clock pulse width low level t
Clock pulse width high level t
EXTAL
t
EXr
Figure 23.5 External Clock Input Timing
Symbol
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
t
EXH
Min.
20
20
0.4
0.4
DEXT
VCC = 3.0 to 3.6 V
cycle, a reset signal should be set to low to
Max.
5
5
0.6
0.6
t
EXf
t
EXL
Unit Test Conditions
ns
ns
ns
ns
t
t
cyc
cyc
DEXT
) has passed. As the clock
V
Figure 23.5
Figure 26.4
CC
× 0.5

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