DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 555

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Channel
Channel 2
Note:
17.3.1
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is internally divided into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among
these three registers are performed automatically in accordance with changes in the bus state, and
they affect the status of internal flags such as ICDRE and ICDRF.
In master transmit mode with the I
performed after start condition detection. When the start condition is detected, previous write data
is ignored. In slave transmit mode, writing should be performed after the slave addresses match
and the TRS bit is automatically changed to 1.
In transmit mode (TRS = 1), transmit data can be written to ICDRT when the ICDRE flag is 1.
After the transmit data has been written to ICDRT, the ICDRE flag is cleared to 0. Then, when
ICDRS becomes empty on completion of the previous transmission, the data are automatically
transferred from ICDRT to ICDRS and the ICDRE flag is set to 1. As long as ICDRS contains
data to be transmitted or data being transmitted, data written to ICDRT are retained there.
In receive mode (TRS = 0), data is not transferred from ICDRT to ICDRS. Thus, do not write to
ICDRT when in this mode.
In receive mode (TRS = 0), data received in ICDRR can be read when the ICDRF flag is 1. After
the data has been read from ICDRR, the ICDRF flag is cleared to 0. Each time ICDRS contains
data on completion of one round of reception, the data is automatically transferred from ICDRS to
* Upper address: when RELOCATE = 0
I
2
Lower address: when RELOCATE = 1
C Bus Data Register (ICDR)
Register Name
I
I
I
I
Second slave address register_2
I
Slave address register_2
I
register_2
2
2
2
2
2
2
C bus extended control register_2
C bus control register_2
C bus status register_2
C bus data register_2
C bus mode register_2
C bus control initialization
2
C bus format, writing transmit data to ICDR should be
Abbreviation R/W
ICXR_2
ICCR_2
ICSR_2
ICDR_2
SARX_2
ICMR_2
SAR_2
ICRES_2
Rev. 3.00 Sep. 28, 2009 Page 509 of 910
R/W H'00
R/W H'00
R/W H'01
R/W H'00
R/W H'00
R/W H'01
R/W ⎯
R/W H'0F
Section 17 I
Initial
Value Address
H'FE8C
H'FE88
H'FE89
H'FE8E
H'FE8E
H'FE8F
H'FE8F
H'FE8A
2
C Bus Interface (IIC)
REJ09B0350-0300
Data Bus
Width
8
8
8
8
8
8
8
8