DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 508

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI)
15.9.6
(1)
= TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode
depend on the port settings, and the pins output a high-level signal after mode is cancelled and
then the TE is set to 1 again. If the transition is made during data transmission, the data being
transmitted will be undefined.
To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR,
write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different
transmission mode, initialize the SCI first.
Figure 15.33 shows a sample flowchart for mode transition during transmission. Figures 15.34 and
15.35 show the pin states during transmission.
Rev. 3.00 Sep. 28, 2009 Page 462 of 910
REJ09B0350-0300
Before making the transition to module stop or software standby, stop all transmit operations (TE
Transmission
Figure 15.33 Sample Flowchart for Mode Transition during Transmission
SCI Operations during Mode Transitions
Cancel software standby mode etc.
software standby mode etc.
Change operating mode?
Read TEND flag in SSR
All data transmitted?
Make transition to
Start transmission
Transmission
Initialization
TEND = 1
Yes
Yes
Yes
TE = 0
[2]
No
No
No
[1]
[3]
TE = 1
[1] Data being transmitted is lost halfway.
[2] Also clear TIE and TEIE to 0 when
[3] Module stop mode and watch mode
Data can be normally transmitted from
the CPU by setting TE to 1, reading
SSR, writing to TDR, and clearing
TDRE to 0 after mode cancellation.
they are 1.
are included.