DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 543

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(5)
Figure 16.10 shows an example of the data reception flowchart.
Data Reception
(Transmission/reception standby flow)
Receive data ready interrupt
Read receive FIFO
PE = 1, or OE = 1
BI = 1, FE = 1,
Read FLSR
Read FLSR
DR = 0
Figure 16.10 Example of Data Reception Flowchart
No
Yes
Error processing
[1]
[2]
[3]
[4]
Section 16 Serial Communication Interface with FIFO (SCIF)
[1] When data is received, a receive data ready
[2] Confirm that the BI, FE, PE, and OE flags in
[3] Read the receive FIFO.
[4] Check the DR flag in FLSR. When the DR flag
interrupt occurs. Go to the data reception flow
by using this interrupt trigger.
FLSR are all cleared. If any one of these flags
is set to 1, perform error processing.
is cleared and all of the data has been read, data
reception is complete.
Rev. 3.00 Sep. 28, 2009 Page 497 of 910
REJ09B0350-0300