DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 655

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
19.3.7
LADR3 sets the LPC channel 3 host address and controls the operation of the bidirectional data
registers. The contents of the address fields in LADR3 must not be changed while channel 3 is
operating (while LPC3E is set to 1).
• LADR3H
• LADR3L
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name Initial Value Slave Host Description
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit Name Initial Value Slave Host Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
TWRE
LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel 3 Address Bits 15 to 8
Set the LPC channel 3 host address.
Channel 3 Address Bits 7 to 3
Set the LPC channel 3 host address.
Reserved
The initial value should not be changed.
Channel 3 Address Bit 1
Sets the LPC channel 3 host address.
Bidirectional Data Register Enable
Enables or disables bidirectional data register
operation.
0: TWR operation is disabled
1: TWR operation is enabled
TWR-related I/O address match determination is
halted
Rev. 3.00 Sep. 28, 2009 Page 609 of 910
Section 19 LPC Interface (LPC)
REJ09B0350-0300

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