DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 412
![IC H8S/2117 MCU FLASH 145TFLGA](/photos/12/20/122098/df2117vlp20v_sml.jpg)
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 412 of 960
- Download datasheet (6Mb)
Section 13 8-Bit Timer (TMR)
13.3.5
TCSR indicates the status flags and controls compare-match output.
• TCSR_0
Rev. 3.00 Sep. 28, 2009 Page 366 of 910
REJ09B0350-0300
Bit
7
6
5
4
3
2
Bit Name
CMFB
CMFA
OVF
ADTE
OS3
OS2
Timer Control/Status Register (TCSR)
Initial
Value
0
0
0
0
0
0
R/W
R/(W)* Compare-Match Flag B
R/(W)* Compare-Match Flag A
R/(W)* Timer Overflow Flag
R/W
R/W
R/W
Description
[Setting condition]
When the values of TCNT_0 and TCORB_0 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
[Setting condition]
When the values of TCNT_0 and TCORA_0 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
[Setting condition]
When TCNT_0 overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
A/D Trigger Enable
Enables or disables A/D converter start requests by
compare-match A.
0: A/D converter start requests by compare-match A
1: A/D converter start requests by compare-match A
Output Select 3 and 2
These bits specify how the TMO0 pin output level is to
be changed by compare-match B of TCORB_0 and
TCNT_0.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
are enabled
are disabled
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