DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 457

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
[Legend]
x:
Bit
7
6
5
4
3
2
1
0
Don't care
Bit Name
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1,a TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
Write 0 to this bit in smart card interface mode.
Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.
Clock Enable 1 and 0
Controls the clock output from the SCK pin. In
GSM mode, clock output can be dynamically
switched. For details, see section 15.7.8, Clock
Output Control.
00: Output disabled (SCK pin functions as I/O port.)
01: Clock output
1x: Reserved
00: Output fixed to low
01: Clock output
10: Output fixed to high
11: Clock output
When GM in SMR = 0
When GM in SMR = 1
Section 15 Serial Communication Interface (SCI)
Rev. 3.00 Sep. 28, 2009 Page 411 of 910
REJ09B0350-0300

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