DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 565

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
1
Bit Name
IRIC
Initial
Value
0
R/W
R/(W)* I
Description
Indicates that the I
interrupt request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
See section 17.4.7, IRIC Setting Timing and SCL
Control. The conditions under which IRIC is set also
differ depending on the setting of the ACKE bit in
ICCR.
[Setting conditions]
All operating modes:
1. When a start condition is detected in transmit mode
2. When data is transferred from ICDRT to ICDRS in
3. When data is transferred from ICDRS to ICDRR in
4. If 1 is received as the acknowledge bit (when the
I
1. When a wait is inserted between the data and
2. When the AL flag is set to 1 after bus arbitration is
I
1. When the slave address (SVA or SVAX) matches
2. When the general call address is detected after the
3. When a stop condition is detected (when the STOP
2
2
2
C Bus Interface Interrupt Request Flag
C bus format master mode:
C bus format slave mode:
and the ICDRE flag is set to 1
transmit mode and the ICDRE flag is set to 1
receive mode and the ICDRF flag is set to 1
ACKE bit is 1 in transmit mode) at the completion of
data transmission
acknowledge bit when the WAIT bit is 1
lost while the ALIE bit is 1
after the reception of the first frame following the
start condition and the AAS flag or AASX flag is set
to 1
reception of the first frame following the start
condition and the ADZ flag is set to 1 (the FS bit in
SAR is 0)
or ESTP flag is set to 1) while the STOPIM bit is 0
Rev. 3.00 Sep. 28, 2009 Page 519 of 910
2
C bus interface has issued an
Section 17 I
2
C Bus Interface (IIC)
REJ09B0350-0300