DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 478

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI)
Rev. 3.00 Sep. 28, 2009 Page 432 of 910
REJ09B0350-0300
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Clear RE bit in SCR to 0
Read RDRF flag in SSR
Read ORER, PER, and
Figure 15.9 Sample Serial Reception Flowchart (1)
PER ∨ FER ∨ ORER = 1
All data received?
FER flags in SSR
Start reception
End reception
Initialization
RDRF = 1
Yes
No
Yes
(Continued on next page)
Error processing
Yes
[1]
[2]
[4]
[5]
[6]
[3]
[1] SCI initialization:
[2] [3] Receive error processing and
[4] SCI status check and receive data
[5] Serial reception continuation
Note:
[Legend]
∨: Logical add (OR)
The RxD pin is automatically
designated as the receive data input
pin.
break detection:
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
appropriate error processing, ensure
that the ORER, PER, and FER flags
are all cleared to 0. Reception cannot
be resumed if any of these flags are
set to 1. In the case of a framing error,
a break can be detected by reading
the value of the input port
corresponding to the RxD pin.
read:
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
procedure:
To continue serial reception, before
the stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
process of [6].
Do not write to SMR, SCR, BRR,
and SDCR from the start to the
end of reception except the