DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 571

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
17.3.6
ICSR consists of status flags. Also see tables 17.5 and 17.6.
Bit
7
6
5
Bit Name
ESTP
STOP
IRTR
I
2
C Bus Status Register (ICSR)
Initial
Value
0
0
0
R/W
R/(W)* Error Stop Condition Detection Flag
R/(W)* Normal Stop Condition Detection Flag
R/(W)* I
Description
This bit is valid in I
[Setting condition]
When a stop condition is detected during frame
transfer.
[Clearing conditions]
This bit is valid in I
[Setting condition]
When a stop condition is detected after frame transfer
completion.
[Clearing conditions]
Request Flag
Indicates that the I
interrupt request to the CPU, and the source is
completion of reception/transmission of one frame.
When the IRTR flag is set to 1, the IRIC flag is also set
to 1 at the same time.
[Setting conditions]
I
Master mode or clocked synchronous serial format
mode with I
[Clearing conditions]
2
2
C Bus Interface Continuous Transfer Interrupt
C bus format slave mode:
When 0 is written in ESTP after reading ESTP = 1
When the IRIC flag in ICCR is cleared to 0
When 0 is written in STOP after reading STOP = 1
When the IRIC flag is cleared to 0
When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
When the ICDRE or ICDRF flag is set to 1
When 0 is written after reading IRTR = 1
When the IRIC flag is cleared to 0 while ICE is 1
2
C bus format:
Rev. 3.00 Sep. 28, 2009 Page 525 of 910
2
2
2
C bus format slave mode.
C bus format slave mode.
C bus interface has issued an
Section 17 I
2
C Bus Interface (IIC)
REJ09B0350-0300

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