DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 528

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 482 of 910
REJ09B0350-0300
Bit
3
2
Bit Name
FE
PE
Initial Value R/W
0
0
R
R
Description
Framing Error
Indicates that the stop bit of the receive data is
invalid. When the FIFO is enabled, this error occurs
in any receive data in the FIFO, and this bit is set
when the receive data is in the first FIFO buffer. The
UART attempts resynchronization after a framing
error occurs. The UART, which assumes that the
framing error is due to the next start bit, samples the
start bit and treats it as a start bit.
0: No framing error
[Clearing condition]
FLSR read
1: A framing error
[Setting condition]
Invalid stop bit in the receive data
Parity Error
This bit indicates a parity error in the receive data
when the PEN bit in FLCR is 1. When the FIFO is
enabled, this error occurs in any receive data in the
FIFO, and this bit is set when the receive data is in
the first FIFO buffer.
0: No parity error
[Clearing condition]
FLSR read
If this bit is set during an overrun error, read FLSR
twice.
1: A parity error
[Setting condition]
Detection of parity error in receive data