DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 698

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 LPC Interface (LPC)
19.6
19.6.1
The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but
an interface protocol that uses the flags in STR must be followed to avoid data conflict. For
example, if the host and slave both try to access IDR or ODR at the same time, the data will be
corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to
data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to
TWR15 has been obtained.
Table 19.12 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3,
TWR0MW, TWR0SW, and TWR1 to TWR15.
Rev. 3.00 Sep. 28, 2009 Page 652 of 910
REJ09B0350-0300
Usage Note
Data Conflict