DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 43

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.5 Usage Notes ....................................................................................................................... 587
Section 19 LPC Interface (LPC) ........................................................................589
19.1 Features.............................................................................................................................. 589
19.2 Input/Output Pins ............................................................................................................... 592
19.3 Register Descriptions ......................................................................................................... 593
19.4 Operation ........................................................................................................................... 635
19.5 Interrupt Sources................................................................................................................ 648
18.5.1 KBIOE Setting and KCLK Falling Edge Detection.............................................. 587
18.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission .................... 588
18.5.3 Module Stop Mode Setting ................................................................................... 588
18.5.4 Medium-Speed Mode............................................................................................ 588
18.5.5 Transmit Completion Flag (KBTE) ...................................................................... 588
19.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 595
19.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 601
19.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 604
19.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 605
19.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L)................ 606
19.3.6 LPC Channel 2 Address Registers H and L (LADR2H and LADR2L)................ 607
19.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 609
19.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 611
19.3.9 Input Data Registers 1 to 4 (IDR1 to IDR4) ......................................................... 612
19.3.10 Output Data Registers 1 to 4 (ODR1 to ODR4).................................................... 612
19.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) ..................................... 613
19.3.12 Status Registers 1 to 4 (STR1 to STR4)................................................................ 613
19.3.13 SERIRQ Control Register 0 (SIRQCR0).............................................................. 620
19.3.14 SERIRQ Control Register 1 (SIRQCR1).............................................................. 624
19.3.15 SERIRQ Control Register 2 (SIRQCR2).............................................................. 628
19.3.16 SERIRQ Control Register 3 (SIRQCR3).............................................................. 631
19.3.17 SERIRQ Control Register 4 (SIRQCR4).............................................................. 632
19.3.18 SCIF Address Register (SCIFADRH, SCIFADRL) ............................................. 633
19.3.19 Host Interface Select Register (HISEL)................................................................ 634
19.4.1 LPC interface Activation ...................................................................................... 635
19.4.2 LPC I/O Cycles ..................................................................................................... 635
19.4.3 Gate A20 ............................................................................................................... 638
19.4.4 LPC Interface Shutdown Function (LPCPD)........................................................ 641
19.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ)...................................... 645
19.4.6 LPC Interface Clock Start Request ....................................................................... 647
19.4.7 SCIF Control from LPC Interface......................................................................... 647
19.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI ..................................................... 648
Rev. 3.00 Sep. 28, 2009 Page xli of xliv
REJ09B0350-0300