DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 693

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

There are two modes⎯continuous mode and quiet mode⎯for serialized interrupts. The mode
initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer
cycle that ended before that cycle.
In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet
mode, the slave with interrupt sources requiring a request can also initiate an interrupt transfer
cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate interrupt
transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the power-down state.
In order for a slave to transfer an interrupt request in this case, a request to restart the clock must
first be issued to the host. For details see section 19.4.6, LPC Interface Clock Start Request.
19.4.6
A request to restart the clock (LCLK) can be sent to the host by means of the CLKRUN pin. With
LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the
transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt
request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to
the host. The timing for this operation is shown in figure 19.7.
Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a
different protocol, using the PME signal, etc.
19.4.7
Setting the SCIFE bit in HICR5 to 1 allows the LPC host to communicate with the SCIF. Then,
the LPC interface can access the registers of the module SCIF other than SCIFCR. For details on
transmission and reception, see section 16, Serial Communication Interface with FIFO (SCIF).
LCLK
CLKRUN
LPC Interface Clock Start Request
SCIF Control from LPC Interface
Pull-up enable
Figure 19.7 Clock Start Request Timing
Driven by the slave processor
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Rev. 3.00 Sep. 28, 2009 Page 647 of 910
Driven by the host processor
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Section 19 LPC Interface (LPC)
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REJ09B0350-0300
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