DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 932

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 26 Electrical Characteristics
26.3.3
Tables 26.7 to 26.9 show the on-chip peripheral module timing. The on-chip peripheral modules
that can be operated by the subclock (φ = 32.768 kHz) are I/O ports, external interrupts (NMI,
IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD) and watchdog timer
(WDT_1) only.
Table 26.7 Timing of On-Chip Peripheral Modules
Conditions:
Rev. 3.00 Sep. 28, 2009 Page 886 of 910
REJ09B0350-0300
Item
I/O ports
TPU
TMR
TCM
TDP
PWMU, PWMX
SCI
Timing of On-Chip Peripheral Modules
V
operating frequency
Output data delay time*
Input data setup time
Input data hold time
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
TCM input setup time
TCM clock input setup time
TCM clock pulse width
TDP input setup time
TDP clock input setup time
TDP clock pulse width
Pulse output delay time
Input clock cycle
Input clock pulse width
CC
= 3.0 V to 3.6 V, V
Single edge
Both edges
Single edge
Both edges
Asynchronous
Synchronous
2
SS
= 0 V, φ = 32.768 kHz*
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PWD
PRS
PRH
TOCD
TICS
TCKS
TCKWH
TCKWL
TMOD
TMRS
TMCS
TMCWH
TMCWL
TCMS
TCMCKS
TCMCKW
TDPS
TDPCKS
TDPCKW
PWOD
Scyc
SCKW
Min.
⎯
30
30
⎯
30
30
1.5
2.5
⎯
30
30
1.5
2.5
30
30
1.5
30
30
1.5
⎯
4
6
0.4
1
, φ = 8 MHz to maximum
Max.
50
⎯
⎯
50
⎯
⎯
⎯
⎯
50
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
50
⎯
⎯
0.6
Unit
ns
ns
t
ns
t
ns
t
ns
t
ns
t
t
cyc
cyc
cyc
cyc
cyc
Scyc
Test
Conditions
Figure 26.9
Figure 26.10
Figure 26.11
Figure 26.12
Figure 26.14
Figure 26.13
Figure 26.15
Figure 26.16
Figure 26.17
Figure 26.18
Figure 26.19
Figure 26.20