DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 836

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 25 List of Registers
Rev. 3.00 Sep. 28, 2009 Page 790 of 910
REJ09B0350-0300
Register Name
PWM duty setting register 0_B
PWM prescaler register 0_B
PWM duty setting register 1_B
PWM prescaler register 1_B
PWM duty setting register 2_B
PWM prescaler register 2_B
PWM duty setting register 3_B
PWM prescaler register 3_B
PWM duty setting register 4_B
PWM prescaler register 4_B
PWM duty setting register 5_B
PWM prescaler register 5_B
PWM control register A_B
PWM control register B_B
PWM control register C_B
PWM control register D_B
Timer control register_1
Timer mode register_1
Timer I/O control register_1
Timer interrupt enable register_1
Timer status register_1
Timer counter _1
Timer general register A_1
Timer general register B_1
LPC channel 1 address register H
LPC channel 1 address register L
LPC channel 2 address register H
LPC channel 2 address register L
SCIF address register H
SCIF address register L
LPC channel 4 address register H
LPC channel 4 address register L
Abbreviation
PWMREG0_B 8
PWMPRE0_B 8
PWMREG1_B 8
PWMPRE1_B 8
PWMREG2_B 8
PWMPRE2_B 8
PWMREG3_B 8
PWMPRE3_B 8
PWMREG4_B 8
PWMPRE4_B 8
PWMREG5_B 8
PWMPRE5_B 8
PWMCONA_B 8
PWMCONB_B 8
PWMCONC_B 8
PWMCOND_B 8
TCR_1
TMDR_1
TIOR_1
TIER_1
TSR_1
TCNT_1
TGRA_1
TGRB_1
LADR1H
LADR1L
LADR2H
LADR2L
SCIFADRH
SCIFADRL
LADR4H
LADR4L
Number
of bits
8
8
8
8
8
16
16
16
8
8
8
8
8
8
8
8
Address
H'FD10
H'FD11
H'FD12
H'FD13
H'FD14
H'FD15
H'FD16
H'FD17
H'FD18
H'FD19
H'FD1A
H'FD1B
H'FD1C
H'FD1D
H'FD1E
H'FD1F
H'FD40
H'FD44
H'FD45
H'FD46
H'FD48
H'FD4A
H'FDC0
H'FDC1
H'FDC2
H'FDC3
H'FDC4
H'FDC5
H'FDD4
H'FDD5
H'FD41
H'FD42
Module
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
LPC
LPC
LPC
LPC
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
PWMU_B 8
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
LPC
LPC
LPC
LPC
Data
Width
8
8
8
8
8
16
16
16
8
8
8
8
8
8
8
8
Access
States
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2