DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 483

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
15.5.2
Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
15.12 shows an example of SCI operation for multiprocessor format reception.
MPIE
RDRF
RDR
value
MPIE
RDRF
RDR
value
Multiprocessor Serial Data Reception
1
1
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Start
bit
Start
bit
0
0
Figure 15.12 Example of SCI Operation in Reception
MPIE = 0
MPIE = 0
D0
D0
ID1
D1
D1
Data (ID1)
Data (ID2)
RXI interrupt
request
(multiprocessor
interrupt)
generated
RXI interrupt
request
(multiprocessor
interrupt)
generated
(a) Data does not match station's ID
D7
D7
(b) Data matches station's ID
MPB
MPB
1
1
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
service routine
Stop
bit
Stop
bit
1
1
Start
bit
Start
bit
0
0
Section 15 Serial Communication Interface (SCI)
D0
D0
If not this station's ID,
MPIE bit is set to 1
again
Matches this station's ID,
so reception continues, and
data is received in RXI
interrupt service routine
D1
D1
Rev. 3.00 Sep. 28, 2009 Page 437 of 910
Data (Data 1)
Data (Data 2)
ID2
ID1
D7
D7
MPB
MPB
0
0
RXI interrupt request is
not generated, and RDR
retains its state
Stop
bit
Stop
bit
1
1
MPIE bit set to 1
again
Idle state
(mark state)
Idle state
(mark state)
REJ09B0350-0300
Data 2
1
1

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