DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 373
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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11.6.5
If the CST bit in TCMCR is set to 1 in cycle measurement mode, and the TCMMDS bit in
TCMCR is cleared, but the selected edge from TCMCYI is detected at the same time, detection of
the selected edge will cause the timer to continue to operate in cycle measurement mode. The
timer will not make the transition to timer mode until the next detection of the selected edge. Thus,
ensure that the CST bit is cleared to 0 in cycle measurement mode.
Figure 11.17 shows the timing of this conflict.
11.6.6
TCMCKI and TCMMCI are multiplexed on the same pin of this LSI. Therefore, the selected
external clock and the TCMMCI signal cannot be used at the same time. Do not make the settings
CKS2 to CKS0 = B'111 and CMMS = B'1.
11.6.7
The module-stop control register can be used to select either continuation or stoppage of TCM
operation in module-stopped mode. The default setting is for TCM operation to stop. TCM
registers become accessible on release from module stop mode. For details, see section 24, Power-
Down Modes.
φ
TCMCYI
Internal write
signal
Input capture
signal
TCMMDS
TCMCNT
TCMICR
Figure 11.17 Conflict between Edge Detection and Clearing of TCMMDS
Conflict between Edge Detection in Cycle Measurement Mode and Clearing of
TCMMDS Bit in TCMCR
Settings of TCMCKI and TCMMCI
Setting for Module Stop Mode
(to Switch from Cycle Measurement Mode to Timer Mode)
M
L
H'0000
TCMCNT cleared at the
first rising edge
M
Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 3.00 Sep. 28, 2009 Page 327 of 910
N
TCMCNT not cleared
N
REJ09B0350-0300
N + 1
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