DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 600

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE
• Internal latches used to retain register read information for setting/clearing flags in ICMR,
• The value of the ICMR bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
(2)
• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
• Basically, other register flags are not cleared either, and so flag clearing measures must be
• When initialization is executed by ICRES, the write data for bits CLR3 to CLR0 is not
• Similarly, when clearing is required again, all the bits must be written to simultaneously in
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or
4. Initialize (re-set) the IIC registers.
Rev. 3.00 Sep. 28, 2009 Page 554 of 910
REJ09B0350-0300
and ICDRF flags)
ICCR, and ICSR
taken as necessary.
taken as necessary.
retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously
using an MOV instruction. Do not use a bit manipulation instruction such as BCLR.
accordance with the setting.
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
ICE bit clearing.
bit to 0, and wait for two transfer rate clock cycles.
ICE bit clearing.
Notes on Initialization
2
C Bus Interface (IIC)