DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 321

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
10.5.3
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers. Buffer operation differs depending on whether TGR has been designated as an input
capture register or as a compare match register. Table 10.18 shows the register combinations used
in buffer operation.
Table 10.18 Register Combinations in Buffer Operation
• When TGR is an output compare register
• When TGR is an input capture register
Channel
0
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. This operation is illustrated in figure 10.16.
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register. This operation is
illustrated in figure 10.17.
Buffer Operation
Buffer register
Buffer register
Input capture
signal
Figure 10.16 Compare Match Buffer Operation
Figure 10.17 Input Capture Buffer Operation
Timer General Register
TGRA_0
TGRB_0
Compare match signal
Timer general
register
Timer general
register
Comparator
Rev. 3.00 Sep. 28, 2009 Page 275 of 910
Section 10 16-Bit Timer Pulse Unit (TPU)
Buffer Register
TGRC_0
TGRD_0
TCNT
TCNT
REJ09B0350-0300

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