AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 90

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

SRAM Configuration
The Am79C971 controller supports SRAM as a FIFO
extension as well as providing a read/write data path to
the SRAM. See Figure 48. The Am79C971 controller
will support up to 128K of SRAM on the Expansion
Bus. See Figure 49.
External SRAM Configuration
The SRAM_SIZE (BCR25, bits 7-0) programs the size
of the external SRAM. SRAM_SIZE can also be pro-
grammed to a smaller value than what is present on the
Expansion Bus.
The external SRAM should be programmed on a 512-
byte boundary. However, there should be no accesses
to the RAM space while the Am79C971 controller is
running. The Am79C971 controller assumes that it
completely owns the SRAM while it is in operation. To
specify how much of the SRAM is allocated to transmit
and how much is allocated to receive, the user should
program SRAM_BND (BCR26, bits 7-0) with the page
boundar y where the receive buffer begins. The
SRAM_BND also should be programmed on a 512-
byte boundary. The transmit buffer space starts at
0000h. It is up to the user or the software driver to split
up the memory for transmit or receive; there is no de-
faulted value. The minimum SRAM size required is four
512-byte pages for each transmit and receive queue,
which limits the SRAM size to be at least 4 Kbytes.
90
Command
Sequence
Byte Program
Chip Erase
Sector Erase
Bus
Write
Cycles
Req’d
4
6
6
First Bus
Write Cycle
5555h
5555h
5555h
Addr
Data
AAh
AAh
AAh
Table 12. Am29Fxxx Flash Command
Second Bus
Write Cycle
2AAAh
2AAAh
2AAAh
Addr
Data
55H
55H
55H
Am79C971
Third Bus
Write Cycle
5555h
5555h
5555h
Addr
The SRAM_BND upon H_RESET will be reset to
0000h. The Am79C971 controller will not have any
transmit buffer space unless SRAM_BND is pro-
grammed. The last configuration parameter necessary
is the clock source used to control the Expansion Bus
interface. This is programmed through the SRAM Inter-
face Control register. The externally driven Expansion
Bus Clock (EBCLK) can be used by specifying a value
of 010h in EBCS (BCR27, bits 5-3). This allows the
user to utilize any clock that may be available.
There are two standard clocks that can be chosen as
well, the PCI clock or the crystal clock used to power
the network MAUs. When the PCI or the crystal clock is
used, the EBCLK does not have to be driven, but it
must be tied to VDD through a resistor. The user must
specify an SRAM clock (BCR27, bits 5-3) that will not
stop unless the Am79C971 controller is stopped. Oth-
erwise, the Am79C971 controller will report buffer over-
flows, underflows, corr upt data, and will hang
eventually.
The user can decide to use a fast clock and then divide
down the frequency to get a better duty-cycle if re-
quired. The choices are a divide by 2 or 4 and is pro-
grammed by the CLK_FAC bits (BCR27, bits 2-0). Note
that the Am79C971 controller does not support an
SRAM frequency above 33 MHz regardless of the clock
and clock factor used.
Data
A0h
80h
80h
Fourth Bus
Write Cycle
5555h
5555h
Addr
PA
Data
AAh
AAh
PD
Fifth Bus
Write Cycle
2AAAh
2AAAh
Addr
Data
55h
55h
Sixth Bus
Write Cycle
5555h
Addr
SA
Data
10h
3h