AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 146

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

11-1
0
CSR89: Chip ID Register Upper
Bit
31-16 RES
15-12 VER
11-0
146
MANFID
ONE
PARTIDU
Name
Manufacturer ID. The 11-bit man-
ufacturer
00000000001b. This code is per
the JEDEC Publication 106-A.
Always a logic 1.
Reserved locations. Read as un-
defined.
Version. This 4-bit pattern is
silicon-revision dependent.
Upper 12 bits of the Am79C971
controller part number, i.e., 0010
0110 0010b (262h).
a different ID as that stored in the
Device ID register in the PCI con-
figuration space.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. PARTID is read
only. Write operations are ig-
nored.
Note that this code is not the
same as the Vendor ID in the PCI
configuration space.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. MANFID is
read only. Write operations are
ignored.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. ONE is read
only. Write operations are ig-
nored.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. VER is read
only. Write operations are ig-
nored.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. PARTIDU is
read only. Write
ignored.
Description
code
operations are
for
P R E L I M I N A R Y
AMD
Am79C971
is
CSR92: Ring Length Conversion
Bit
31-16 RES
15-0
CSR100: Bus Timeout
Bit
31-16 RES
15-0
RCON
MERRTO
Name
Name
This register contains the value of
Reserved locations. Written as
zeros and read as undefined.
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an encod-
ed value as found in the initializa-
tion block to a two’s complement
value used for internal counting.
By writing bits 15-12 with an en-
coded ring length, a two’s com-
plemented value is read. The
RCON register is undefined until
written.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Reserved locations. Written as
zeros and read as undefined.
the longest allowable bus latency
(interval between assertion of
REQ and assertion of GNT) that a
system
Am79C971
transfer. If this value of bus laten-
cy is exceeded, then a MERR will
be indicated in CSR0, bit 11, and
an interrupt may be generated,
depending upon the setting of the
MERRM bit (CSR3, bit 11) and
the IENA bit (CSR0, bit 6).
The value in this register is inter-
preted as the unsigned number of
XTAL1 clock periods divided by
two, (i.e., the value in this register
is given in 0.1 s increments.) For
example, the value 0600h (1536
decimal) will cause a MERR to be
indicated after 153.6 s of bus la-
tency. A value of 0 will allow an
infinitely long bus latency, i.e.,
bus timeout error will never oc-
cur.
Description
Description
may
controller
insert
into
master
an