AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 122

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

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ASTRP_RCV Auto Strip Receive. When set,
MFCO
MFCOM
UINTCMD
UINT
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
Read/Write accessible always.
ASTRP_RCV
H_RESET or S_RESET and is
unaffected by the STOP bit.
is set by the Am79C971 control-
ler when the Missed Frame
Counter (CSR112 and CSR114)
has wrapped around.
When MFCO is set, INTA is as-
serted if IENA is 1 and the mask
bit MFCOM is 0.
Read/Write accessible always.
MFCO is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Mask. If MFCOM is set, the
MFCO bit will be masked and un-
able to set the INTR bit.
Read/Write accessible always.
MFCOM is set to 1 by H_RESET
or S_RESET and is not affected
by the STOP bit.
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1.
UINTCMD will be cleared inter-
nally after the Am79C971 control-
ler has set UINT to 1.
Read/Write accessible always.
UINTCMD
H_RESET or S_RESET or by
setting the STOP bit.
Am79C971 controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
Missed Frame Counter Overflow
Missed Frame Counter Overflow
User
User Interrupt. UINT is set by the
MFCO
Interrupt
is
is
is
cleared
cleared
cleared
Command.
Am79C971
by
by
by
5
4
3
2
RCVCCO
RCVCCOM Receive Collision Counter Over-
TXSTRT
TXSTRTM
Read/Write accessible always.
UINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET or S_RESET or by
setting the STOP bit.
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
Read/Write accessible always.
RCVCCO is cleared by the host
by writing a 1. Writing a 0 has no
effect. RCVCCO is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
Read/Write accessible always.
RCVCCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
Read/Write accessible always.
TXSTRT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. TXSTRT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
Read/Write accessible always.
TXSTRTM
H_RESET or S_RESET and is
not affected by the STOP bit.
Receive Collision Counter Over-
flow is set by the Am79C971 con-
troller when the Receive Collision
Counter (CSR114 and CSR115)
has wrapped around.
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
Am79C971 controller whenever it
begins transmission of a frame.
STRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
Transmit Start status is set by the
Transmit Start Mask. If TX-
UINT
is
is
set
cleared
to
1
by
by