AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 177

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

BCR32: MII Control and Status Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15
14
ANTST
MIIPD
Name
Reserved locations. Written as
zeros and read as undefined.
Reserved. Reserved for manu-
facturing tests. Written as 0 and
read as undefined.
MII PHY Detect. MIIPD reflects
the quiescent state of the MDIO
pin. MIIPD is continuously updat-
ed whenever there is no manage-
ment operation in progress on the
MII interface. When a manage-
ment operation begins on the in-
terface, the state of MIIPD is
preserved until the operation
ends, when the quiescent state is
again monitored and continuous-
ly updates the MIIPD bit. When
the MDIO pin is at a quiescent
LOW state, MIIPD is cleared to 0.
When the MDIO pin is at a quies-
cent HIGH state, MIIPD is set to
1. MIIPD is used by the automatic
port selection logic to select the
MII port. When the Auto Select bit
(ASEL, BCR2, bit 1) is a 1 and the
MIIPD bit is a 1, the MII port is se-
lected. Any transition on the MI-
The STVAL value is interpreted
as an unsigned number with a
resolution of 12.8
stance, a value of 122 ms would
be programmed with a value of
9531 (253Bh). A value of 0 is un-
defined and will result in erratic
behavior.
Read and write accessible al-
ways. STVAL is set to FFFFh af-
ter H_RESET and is unaffected
by S_RESET and the STOP bit.
Note: Use of this bit will cause
data corruption and erroneous
operation.
Read/Write accessible always.
ANTST is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit.
Description
P R E L I M I N A R Y
s. For in-
Am79C971
13-12 FMDC
11
FMDC
00
01
10
11
APEP
Table 40. FMDC Values
Fast Management Data Clock
2.5 MHz
5 MHz
10 MHz
Reserved
IPD bit will set the MIIPDINT bit in
CSR7, bit 1.
Read accessible always. MIIPD
is read only. Write operations are
ignored.
Fast Management Data Clock.
When FMDC is set to 2h the MII
Management Data Clock will run
at 10 MHz. The Management
Data Clock will no longer be IEEE
802.3u-compliant and setting this
bit should be used with care. The
accompanying
must also be able to accept man-
agement frames at the new clock
rate. When FMDC is set to 1h, the
MII Management Data Clock will
run at 5 MHz. The Management
Data Clock will no longer be IEEE
802.3u-compliant and setting this
bit should be used with care. The
accompanying
must also be able to accept man-
agement frames at the new clock
rate. When FMDC is set to 0h, the
MII Management Data Clock will
run at 2.5 MHz and will be fully
compliant to IEEE 802.3u stan-
dards.
Read/Write accessible always.
FMDC
H_RESET, and is unaffected by
S_RESET and the STOP bit
MII
APEP
Am79C971 controller will poll the
MII status register in the external
PHY. This feature allows the soft-
ware driver or upper layers to see
any changes in the status of the
external PHY. An interrupt when
enabled is generated when the
contents of the new status is dif-
ferent from the previous status.
Auto-Poll will not function when
the internal PHY is selected.
Auto-Poll
when
is
set
set
External
external
external
to
to
0
1
during
PHY.
PHY
PHY
177
the