AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 67

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

If DRCVBC (CSR15, bit 14) is cleared to 0, only BAM,
but not LAFM will be set when a Broadcast frame is re-
ceived, even if the Logical Address Filter is pro-
grammed in such a way that a Broadcast frame would
pass the hash filter. If DRCVBC is set to 1 and the Log-
ical Address Filter is programmed in such a way that a
Broadcast frame would pass the hash filter, LAFM will
be set on the reception of a Broadcast frame.
When the Am79C971 controller operates in promiscu-
ous mode and none of the three match bits is set, it is
an indication that the Am79C971 controller only ac-
cepted the frame because it was in promiscuous mode.
When the Am79C971 controller is not programmed to
be in promiscuous mode, but the EADI interface is en-
abled, then when none of the three match bits is set, it
is an indication that the Am79C971 controller only ac-
cepted the frame because it was not rejected by driving
the EAR pin LOW within 64 bytes after SFD.
See Table 6 for receive address matches.
Automatic Pad Stripping
During reception of an IEEE 802.3 frame, the pad field
can be stripped automatically. Setting ASTRP_RCV
(CSR4, bit 0) to 1 enables the automatic pad stripping
feature. The pad field will be stripped before the frame
is passed to the FIFO, thus preserving FIFO space for
additional frames. The FCS field will also be stripped,
since it is computed at the transmitting station based on
the data and pad field characters, and will be invalid for
a receive frame that has had the pad characters
stripped.
Increasing Time
1010....1010
Preamble
Start of Frame
at Time = 0
Bits
56
Figure 34. IEEE 802.3 Frame And Length Field Transmission Order
10101011
SFD
Bits
8
Destination
Address
Bytes
6
Bit
0
Am79C971
Address
Source
Bytes
Significant
6
Most
Byte
The number of bytes to be stripped is calculated from
the embedded length field (as defined in the ISO 8802-
3 (IEEE/ANSI 802.3) definition) contained in the frame.
The length indicates the actual number of LLC data
bytes contained in the message. Any received frame
which contains a length field less than 46 bytes will have
the pad field stripped (if ASTRP_RCV is set). Receive
frames which have a length field of 46 bytes or greater
will be passed to the host unmodified.
Figure 34 shows the byte/bit ordering of the received
length field for an IEEE 802.3-compatible frame format.
PAM
Bit
0
1
0
0
0
Length
7
Bytes
2
Bit
0
LAF
Table 6. Receive Address Match
M
0
0
1
1
0
Significant
1 – 1500
Bytes
Least
Data
Byte
LLC
BAM DRC
46 – 1500
Bytes
0
0
0
0
1
Bit
7
45 – 0
Bytes
Pad
VBC
X
X
0
1
0
Comment
Frame accepted due
to PROM = 1 or no
EADI reject
Physical address
match
Logical address filter
match;
frame is not of type
broadcast
Logical address filter
match;
frame can be of type
broadcast
Broadcast frame
Bytes
FCS
4
20550D-37
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