AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 238

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

Setup
The driver should set up descriptors in groups of three,
with the OWN and STP bits of each set of three de-
scriptors to read as follows: 11b, 10b, 00b.
An option bit (LAPPEN) exists in CSR3, bit position 5;
the software should set this bit. When set, the LAPPEN
bit directs the Am79C971 controller to generate an IN-
TERRUPT when STP has been written to a receive de-
scriptor by the Am79C971 controller.
Flow
The Am79C971 controller polls the current receive de-
scriptor at some point in time before a message arrives.
The Am79C971 controller determines that this receive
buffer is OWNed by the Am79C971 controller and it
stores the descriptor information to be used when a
message does arrive.
N0
N1
C0
C1
S1
C2
C3
S1
C4
Note: Even though the third buffer is not owned by the
Am79C971 controller, existing AMD Ethernet control-
lers will continue to perform data DMA into the buffer
D-2
Frame preamble appears on the wire, followed
by SFD and destination address.
The 64th byte of frame data arrives from the
wire. This causes the Am79C971 controller to
begin frame data DMA operations to the first
buffer.
When the 64th byte of the message arrives, the
Am79C971 controller performs a lookahead
operation to the next receive descriptor. This
descriptor should be owned by the Am79C971
controller.
The Am79C971 controller intermittently re-
quests the bus to transfer frame data to the first
buffer as it arrives on the wire.
The driver remains idle.
When the Am79C971 controller has completely
filled the first buffer, it writes status to the first
descriptor.
When the first descriptor for the frame has been
written,
Am79C971
Am79C971 controller will generate an SRP IN-
TERRUPT. (This interrupt appears as a RINT
interrupt in CSR0).
The SRP INTERRUPT causes the CPU to
switch tasks to allow the Am79C971 controller’s
driver to run.
During the CPU interrupt-generated task
switching, the Am79C971 controller is perform-
ing a lookahead operation to the third descrip-
tor. At this point in time, the third descriptor is
owned by the CPU.
changing
controller
ownership
to
the
CPU,
from
the
the
Am79C971
space that the controller already owns (i.e., buffer num-
ber 2). The controller does not know if buffer space in
buffer number 2 will be sufficient or not for this frame,
but it has no way to tell except by trying to move the en-
tire message into that space. Only when the message
does not fit will it signal a buffer error condition--there is
no need to panic at this point that it discovers that it
does not yet own descriptor number 3.
S2
S3
C5
S4
S5
C6
C7
The first task of the drivers interrupt service
routing is to collect the header information from
the Am79C971 controller’s first buffer and pass
it to the application.
The application will return an application buffer
pointer to the driver. The driver will add an offset
to the application data buffer pointer, since the
Am79C971 controller will be placing the first
portion of the message into the first and second
buffers. (the modified application data buffer
pointer will only be directly used by the
Am79C971 controller when it reaches the third
buffer.) The driver will place the modified data
buffer pointer into the final descriptor of the
group (#3) and will grant ownership of this de-
scriptor to the Am79C971 controller.
Interleaved with S2, S3, and S4 driver activity,
the Am79C971 controller will write frame data
to buffer number 2.
The driver will next proceed to copy the con-
tents of the Am79C971 controller’s first buffer
to the beginning of the application space. This
copy will be to the exact (unmodified) buffer
pointer that was passed by the application.
After copying all of the data from the first buffer
into the beginning of the application data buffer,
the driver will begin to poll the ownership bit of
the second descriptor. The driver is waiting for
the Am79C971 controller to finish filling the sec-
ond buffer.
At this point, knowing that it had not previously
owned the third descriptor and knowing that the
current message has not ended (there is more
data in the FIFO), the Am79C971 controller will
make a last ditch lookahead to the final (third)
descriptor. This time the ownership will be
TRUE (i.e., the descriptor belongs tot he con-
troller), because the driver wrote the application
pointer into this descriptor and then changed
the ownership to give the descriptor to the
Am79C971 controller back at S3. Note that if
steps S1, S2, and S3 have not completed at
this time, a BUFF error will result.
After filling the second buffer and performing
the last chance lookahead to the next descrip-
tor, the Am79C971 controller will write the sta-