AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 89

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

The EROMCS is driven low for the value ROMTMG +
1. Figure 46 assumes that ROMTMG is set to nine.
EBD[7:0] is sampled with the next rising edge of CLK
ten clock cycles after EBUA_EBA[7:0] was driven with
a new address value. This PCI slave access to the
Flash/EPROM will result in a retry for the very first ac-
cess. Subsequent accesses may give a retry or not, de-
pending on whether or not the data is present and valid.
The access time is dependent on the ROMTMG bits
(BCR18, bits 15-12) and the Flash/EPROM. This ac-
cess mechanism differs from the Expansion ROM ac-
cess mechanism since only one byte is read in this
manner, instead of the 4 bytes in an Expansion ROM
access. The PCI bus will not be held during accesses
through the Expansion Bus Data Port. If the LAAINC
(BCR29, bit 15) is set, the EBADDRL address will be
AMD Flash Programming
AMD’s Flash products are programmed on a byte-by-
byte basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed
by the program set-up command and data write cycles.
Addresses are latched on the falling edge of EBWE
and the data is latched on the rising edge of EBWE.
The rising edge of EBWE begins programming.
Upon executing the AMD Flash Embedded Program
Algorithm command sequence, the Am79C971 con-
troller is not required to provide further controls or tim-
ing. The AMD Flash product will compliment EBD[7]
during a read of the programmed location until the pro-
gramming is complete. The host software should poll
the programmed address until EBD[7] matches the
programmed value.
AMD Flash byte programming is allowed in any se-
quence and across sector boundaries. Note that a data
0 cannot be programmed back to a 1. Only erase oper-
ations can convert zeros to ones. AMD Flash chip
erase is a six-bus cycle operation. There are two unlock
write cycles, followed by writing the set-up command.
Two more unlock cycles are then followed by the chip
erase command. Chip erase does not require the user
to program the device prior to erasure. Upon executing
EBUA_EBA[7:0]
Figure 47. Flash Write from Expansion Bus Data Port
EBDA[15:8]
AS_EBOE
EROMCS
EBD[7:0]
EBWE
CLK
EBUA[19:16]
1
Am79C971
2
3
4
incremented and a continuous series of reads from the
Expansion Data Port (EBDATA, BCR30) is possible.
The address incrementor will roll over without warning
and without incrementing the upper address EBAD-
DRU.
The Flash write is almost the same procedure as the
read access, except that the Am79C971 controller will
not drive AS_EBOE low. The EROMCS and EBWE are
driven low for the value ROMTMG again. The write to
the FLASH port is a posted write and will not result in a
retry to the PCI unless the host tries to write a new
value before the previous write is complete, then the
host will experience a retry. The FLASH can only be ac-
cessed while in STOP or when the SRAM_SIZE = 0
(BCR25, bits 7-0). See Figure 47.
the AMD Flash Embedded Erase Algorithm command
sequence, the Flash device will program and verify the
entire memory for an all zero data pattern prior to elec-
trical erase. The Am79C971 controller is not required
to provide any controls or timings during these opera-
tions. The automatic erase begins on the rising edge of
the last EBWE pulse in the command sequence and
terminates when the data on EBD[7] is 1, at which time
the Flash device returns to the read mode. Polling by
the Am79C971 controller is not required during the
erase sequence. The following FLASH programming-
table excerpt (Table 12) shows the command sequence
for byte programming and sector/chip erasure on an
AMD Flash device. In the following table, PA and PD
stand for programmed address and programmed data,
and SA stands for sector address.
The Am79C971 controller will support only a single
sector erase per command and not concurrent sector
erasures. The Am79C971 controller will support most
FLASH devices as long as there is no timing require-
ment between the completion of commands. The
FLASH access time cannot be guaranteed with the
Am79C971 controller access mechanism. The
Am79C971 controller will also support only Flash de-
vices that do not require data hold times after write op-
erations.
5
6
7
EBDA[15:8]
EBA[7:0]
8
9
10
11
12 13
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