AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 130

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

15-0
CSR13: Physical Address Register 1
Bit
31-16
15-0
CSR14: Physical Address Register 2
Bit
31-16
15-0
CSR15: Mode
This register’s fields are loaded during the Am79C971
controller initialization routine with the corresponding
130
PADR[31:16] Physical
PADR[47:32] Physical
PADR[15:0] Physical
Name
RES
Name
RES
PADR[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
PADR[31:16]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
PADR[47:32]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Address
Address
Address
Register,
Register,
Register,
Am79C971
Initialization Block values, or when a direct register
write has been performed on this register.
Bit
31-16 RES
15
14
13
12
11
Name
PROM
DRCVBC
DRCVPA
DLNKTST
DAPC
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Description
zeros and read as undefined.
PROM = 1, all incoming receive
frames are accepted.
Disable
When
Am79C971 controller from re-
ceiving
Used for protocols that do not
support broadcast addressing,
except as a function of multicast.
DRCVBC is cleared by activation
of
(broadcast messages will be re-
ceived) and is unaffected by
STOP.
Disable Receive Physical Ad-
dress. When set, the physical ad-
dress detection (Station or node
ID) of the Am79C971 controller
will be disabled. Frames ad-
dressed to the nodes individual
physical address will not be rec-
ognized.
Disable
DLNKTST = 1, monitoring of Link
Pulses
DLNKTST = 0, monitoring of Link
Pulses is enabled. This bit only
has meaning when the 10BASE-
T network interface is selected.
rection. When DAPC = 1, the
Reserved locations. Written as
Promiscuous
Disable Automatic Polarity Cor-
H_RESET
broadcast
set,
is
Link
Receive
disabled.
Mode.
Status.
disables
or
messages.
Broadcast.
S_RESET
When
When
When
the