AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 144

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

9-8
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XMTSP[1:0]
Table 28. Transmit Start Point Programming
XMTFW[1:0] Transmit FIFO Watermark. XMT-
00
01
10
00
01
10
11
11
SRAM_SIZE
When an external SRAM is used,
SRAM_SIZE > 0, there is a re-
striction that the number of bytes
written is a combination of bytes
written into the Bus Transmit
FIFO and the MAC Transmit
FIFO. The Am79C971 controller
supports a mode that will wait un-
til a full packet is available before
commencing with the transmis-
sion of preamble. This mode is
useful in a system where high la-
tencies cannot be avoided. See
Table 28.
FW specifies the point at which
transmit
based upon the number of bytes
that could be written to the Trans-
mit FIFO without FIFO overflow.
Transmit DMA is requested at
any time when the number of
bytes specified by XMTFW could
be written to the FIFO without
causing Transmit FIFO overflow,
and the internal microcode en-
gine has reached a point where
the Transmit FIFO is checked to
determine if DMA servicing is re-
quired.
NOTE: A “No SRAM configuration” is
only valid for 10Mb mode. In 100Mb
mode, SRAM is mandatory and must
always be used.
Read/Write accessible only when
either the STOP or the SPND bit
is set. XMTSP is set to a value of
01b (64 bytes) after H_RESET or
S_RESET and is unaffected by
STOP.
>0
>0
>0
>0
0
0
0
0
DMA
Bytes Written
Full Packet
is
128
248
128
20
64
44
64
P R E L I M I N A R Y
requested,
Am79C971
7-0
CSR82: Transmit Descriptor Address Pointer Lower
Bit
31-16 RES
Table 29. Transmit Watermark Programming
XMTFW[1:0]
DMATC[7:0] DMA Transfer Counter. Writing
Name
00
01
10
11
When operating in the NO-SRAM
mode
SRAM_SIZE set to 0, the Bus
Transmit FIFO and the MAC
Transmit FIFO operate like a sin-
gle FIFO and the watermark val-
ue selected by XMTFW[1:0] sets
the number of FIFO byte loca-
tions that must be available in the
FIFO before receive DMA is re-
quested.
NOTE: A “No SRAM configura-
tion” is only valid for 10Mb mode.
In 100Mb mode, SRAM is man-
datory and must always be used.
When operating with an external
SRAM, the Bus Transmit FIFO
and the MAC Transmit FIFO op-
erate independently on the bus
side and MAC side of the external
SRAM, respectively. In this case,
the watermark value set by XMT-
FW[1:0] sets the number of FIFO
byte locations that must be avail-
able in the Bus Transmit FIFO.
See Table 29.
Read/Write accessible only when
either the STOP or the SPND bit
is set. XMTFW is set to a value of
00b (16 bytes) after H_RESET or
S_RESET and is unaffected by
STOP.
and reading to this field has no ef-
fect.
MIN_GNT in the PCI configura-
tion space.
Reserved locations. Written as
zeros and read as undefined.
Description
Use
(no
Bytes Available
Reserved
SRAM
MAX_LAT
108
16
64
present),
and