AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 127

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

12
11
10
RXDPOLL
STINT
STINTE
Read/Write accessible always.
RDMD is set by writing a 1. Writ-
ing a 0 has no effect. RDMD will
be cleared by the Buffer Manage-
ment Unit when it fetches a re-
ceive
cleared by H_RESET. RDMD is
unaffected by S_RESET or by
setting the STOP bit.
POLL is set, the Buffer Manage-
ment Unit will disable receive
polling. Likewise, if RXDPOLL is
cleared, automatic receive poll-
ing is enabled. If RXDPOLL is
set, RDMD bit in CSR7 must be
set in order to initiate a manual
poll of a receive descriptor. Re-
ceive Descriptor Polling will not
take place if RXON is reset.
Read/Write accessible always.
RXDPOLL
H_RESET. RXDPOLL is unaf-
fected by S_RESET or by setting
the STOP bit.
Software Timer interrupt is set by
the Am79C971 controller when
the Software Timer counts down
to 0. The Software Timer will im-
mediately load the STVAL (BCR
31, bits 5-0) into the Software
Timer and begin counting down.
When STINT is set to 1, INTA is
asserted if the enable bit STINTE
is set to 1.
Read/Write accessible always.
STINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
If STINTE is set, the STINT bit
will be able to set the INTR bit.
Read/Write accessible always.
STINTE is set to 0 by H_RESET
and is not affected by S_RESET
or setting the STOP bit
Receive Disable Polling. If RXD-
Software Timer Interrupt. The
Software Timer Interrupt Enable.
STINT
Descriptor.
is
is
cleared
cleared
RDMD
Am79C971
by
by
is
9
8
7
MREINT
MREINTE
MAPINT
When MREINT is set to 1, INTA is
asserted if the enable bit MREIN-
TE is set to 1.
Read/Write accessible always.
MREINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. MREINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Read/Write accessible always.
MREINTE
H_RESET and is not affected by
S_RESET or setting the STOP bit
MII Management Read Error In-
terrupt. The MII Read Error inter-
rupt is set by the Am79C971
controller to indicate that the cur-
rently read register from the ex-
ternal
contents of BCR34 are incorrect
and that the operation should be
performed again. The indication
of an incorrect read comes from
the PHY. During the read turn-
around time of the MII manage-
ment frame the external PHY
should drive the MDIO pin to a
LOW state. If this does not hap-
pen, it indicates that the PHY and
the Am79C971 controller have
lost synchronization.
MII Management Read Error In-
terrupt Enable. If MREINTE is
set, the MREINT bit will be able to
set the INTR bit.
rupt. The MII Auto-Poll interrupt is
set by the Am79C971 controller
to indicate that the currently read
status does not match the stored
previous
change in state for the external
PHY. A change in the Auto-Poll
Access Method (BCR32, Bit 10)
will reset the shadow register and
will not cause an interrupt on the
first access from the Auto-Poll
section. Subsequent accesses
will generate an interrupt if the
shadow register and the read
register produce differences.
MII Management Auto-Poll Inter-
PHY
status
is
is
set
invalid.
indicating
to
0
127
The
by
a