AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 78

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

The MII Management Interface has a built-in detection
system to allow the Am79C971 controller to determine
if an external PHY is attached. The MDIO I/O pin has a
resistor network between the Am79C971 controller and
the external PHY that will assert a static 1 when
connected. If there is no external PHY connected, the
resistor network will drive a static zero. This information
is signaled by the interrupt MPDTINT (CSR7, MIIPDTI,
bit 1), and the status is provided by reading the Media
Independent Interface PHY Detected (MIIPD) (BCR32,
bit 14). This resistor network is only required on an
exposed MII connector.
MII Management Frames
MII management frames are automatically generated
by the Am79C971 controller and conform to the MII
clause in the IEEE 802.3u standard.
This is followed by a start field (ST) and an operation
field (OP). The operation field (OP) indicates whether
the Am79C971 controller is initiating a read or write op-
eration. This is followed by the external PHY address
(PHYAD) and the register address (REGAD) pro-
grammed in BCR33. The internal PHYAD is at location
1Fh and the internal register address space REGAD is
00h - 08h. The external PHY may have a larger ad-
dress space starting at 10h - 1Fh. This is the address
range set aside by the IEEE as vendor usable address
space and will vary from vendor to vendor. This field is
followed by a bus turnaround field. During a read oper-
ation, the bus turnaround field is used to determine if
the external PHY is responding correctly to the read re-
quest or not. The Am79C971 controller will tri-state the
MDIO for both MDC cycles. During the second cycle, if
the external PHY is synchronized to the Am79C971
controller, the external PHY will drive a 0. If the external
PHY does not drive a 0, the Am79C971 controller will
signal a MREINT (CSR7, bit 9) interrupt, if MREINTE
(CSR7, bit 8) is set to a 1, indicating the Am79C971
controller had an MII management frame read error
and that the data in BCR34 is not valid. The data field
to/from the internal or external PHY is read or written
into the BCR34 register. The last field is an IDLE field
that is necessary to give ample time for drivers to turn
off before the next access. The Am79C971 controller
78
1111....1111
Preamb le
Bits
32
Figure 39. Frame Format at the MII Interface Connection
ST
01
Bits
2
10 Rd
01 Wr
OP
Bits
2
Address
PHY
Bits
5
Am79C971
The start of the frame is a preamble of 32 ones and
guarantees that all of the external PHYs are synchro-
nized on the same interface. (See Figure 39.) Loss of
synchronization is possible due to the hot-plugging ca-
pability of the exposed MII.
The IEEE 802.3 specification allows you to drop the
preamble, if after reading the MII Status Register from
the external PHY you can determine that the external
PHY will support Preamble Suppression (BCR34, bit
6). After having a valid MII Status Register read, the
Am79C971 controller will then drop the creation of the
preamble stream until a reset occurs, receives a read
error, or the external PHY is disconnected.
will drive the MDC to 0 and tri-state the MDIO anytime
the MII Management Port is not active.
To help to speed up the reading and writing of the MII
management frames to the external PHY, the MDC can
be sped up to 10 MHz by setting the FMDC bits in
BCR32. The IEEE 802.3 specification requires use of
the 2.5-MHz clock rate, but 5 MHz and 10 MHz are
available for the user. The intended applications are
that the 10-MHz clock rate can be used for a single ex-
ternal PHY on an adapter card or motherboard. The 5-
MHz clock rate can be used for an exposed MII with
one external PHY attached. The 2.5-MHz clock rate is
intended to be used when multiple external PHYs are
connected to the MII Management Port or if compli-
ance to the IEEE 802.3u standard is required.
Auto-Poll External PHY Status Polling
As defined in the IEEE 802.3 standard, the external
PHY attached to the Am79C971 controller’s MII has no
way of communicating important timely status informa-
tion back to Am79C971 controller. The Am79C971
controller has no way of knowing that an external PHY
has undergone a change in status without polling the
MII status register. To prevent problems from occurring
with i nadequate ho st or softwar e po lling, the
Am79C971 controller will Auto-Poll when APEP
(BCR32, bit 11) is set to 1 to insure that the most cur-
rent information is available. See Appendix E, Auto Ne-
Register
Address
Bits
5
Z0 Rd
10 Wr
Bits
TA
2
Data
Bits
16
Idle
Z
Bit
1
miiframe
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