AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 81

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

external PHY is attached to the MII Management Inter-
face, then the DANAS (BCR32, bit 7) bit must be set to
1 and then all configuration control should revert to
software. The Am79C971 controller will read the MII
Status register of the external PHY to determine its sta-
tus and network capabilities. See Appendix E for the bit
descriptions of the MII Status register. If the external
PHY is Auto-Negotiation capable and/or the XPHYANE
(BCR32, bit 5) bit is set to 1, then the Am79C971 con-
troller will start the external PHY’s Auto-Negotiation
process. The Am79C971 controller will write to the ex-
ternal PHY’s Advertisement register with the following
conditions set: turn off the Next Pages support, set the
Technology Ability Field (See Appendix E for the Auto-
Negotiation register bit descriptions) from the external
PHY MII Status register read, and set the Type Selector
field to the IEEE 802.3 standard. The Am79C971 con-
troller will then write to the external PHY’s MII Control
register instructing the external PHY to negotiate the
link. The Am79C971 controller will poll the external
PHY’s MII Status register until the Auto-Negotiation
Complete bit is set to 1and the Link Status bit is set to
1. The Am79C971 controller will then wait a specific
time and then again read the external PHY’s MII Status
register. If the Am79C971 controller sees that the exter-
nal PHY’s link is down, it will try to bring up the external
PHY’s link manually as described above. A new read of
the external PHY’s MII Status register will be made to
see if the link is up. If the link does not come up as pro-
grammed after a specific time, the Am79C971 control-
ler will fail the external PHY link and start the process
again for the internal PHY. If the link has failed, the AUI
is enabled, but the Network Port Manager will still query
the external PHY for an active link.
Automatic Network Selection: Working with the
Micro Linear 6692
The final case that occurs is the hybrid condition that
does not fit neither the Auto-Negotiable case nor the
Non-Auto-Negotiable case. An example of this case is
the Micro Linear 6692 PHY. The Micro Linear 6692
PHY masquerades as an Auto-Negotiable PHY by pro-
viding Auto-Negotiation capabilities, but does not pro-
vide the 10BASE-T MAU. It relies on the MAC
controller, the Am79C971 controller in this case, to pro-
vide the 10BASE-T MAU for it. The Network Port Man-
ager handles this condition virtually the same way as
the Auto-Negotiable case, except for the final hand-
shake that enables the internal 10BASE-T MAU. After
the 6692 negotiates for the 10BASE-T MAU, it monitors
the link for Normal LInk Pulses (NLPs). If it sees the
NLPs, then it will report that it completed the Auto-Ne-
gotiation process. The Am79C971 controller will read
the MII and Auto-Negotiation registers to figure out
which port has been negotiated. At this point, the Net-
work Port Manager will enable the internal 10BASE-T
MAU, if that port has been negotiated, and complete
the first part of the handshake. The final part of the
Am79C971
handshake is to prevent the 6692 from renegotiating
the link without the Network Port Manager’s knowl-
edge. Connecting the LED0 pin to the 10BTRCV pin of
the 6692 will accomplish this. The LED0 reports the link
status from the internal TMAU. The Network Port Man-
ager monitors the internal link status, and knowing
when the 6692 will start to renegotiate the link, it will
stay in synchronization with the 6692.
Automatic Network Selection: Force External Reset
If the XPHYRST bit (BCR32, bit 6) is set to 1, then the
external case flow changes slightly. The Am79C971
controller will write to the external PHY’s MII Control
register with the RESET bit set to 1 (See Appendix E,
Auto Negotiation Registers, for the MII register bit de-
scriptions). This will force a complete reset of the exter-
nal PHY. The Am79C971 controller after a specific time
will poll the external PHY’s MII Control register to see if
the RESET bit is 0. After the RESET bit is cleared, then
the normal flow continues.
External Address Detection Interface
(EADI)
The EADI is provided to allow external address filtering
and to provide a Receive Frame Tag word for propri-
etary routing information. It is selected by setting the
EADISEL bit in BCR2 to 1. This feature is typically uti-
lized by terminal servers, bridges and/or router prod-
ucts. The EADI interface can be used in conjunction
with external logic to capture the packet destination ad-
dress from the serial bit stream as it arrives at the
Am79C971 controller, to compare the captured ad-
dress with a table of stored addresses or identifiers,
and then to determine whether or not the Am79C971
controller should accept the packet.
External Address Detection Interface: Internal PHY
The EADI interface outputs are delivered directly from
the NRZ decoded data and clock recovered by the
Manchester decoder. This allows the external address
detection to be performed in parallel with frame recep-
tion and address comparison in the MAC Station Ad-
dress Detection (SAD) block of the Am79C971
controller.
SRDCLK is provided to allow clocking of the receive bit
stream into the external address detection logic. Note
that when the 10BASE-T port is selected, transitions on
SRDCLK will only occur during receive activity. When
the AUI port is selected, transitions on SRDCLK will
occur during both transmit and receive activity. Once a
received frame commences and data and clock are
available from the decoder, the EADI logic will monitor
the alternating (“1,0”) preamble pattern until the two 1s
of the Start Frame Delimiter (SFD, 10101011 bit pat-
tern) are detected, at which point the SFBD output will
be driven HIGH.
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