AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 71

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

Receiver Path
The principal functions of the receiver are to signal the
Am79C971 controller that there is information on the
receive pair and to separate the incoming Manchester
encoded data stream into clock and NRZ data.
The receiver section consists of two parallel paths (see
Figure 35). The receive data path is a zero threshold,
wide bandwidth line receiver. The carrier path is an off-
set threshold, bandpass detecting line receiver. Both
receivers share common bias networks to allow opera-
tion over a wide input common mode range.
Input Signal Conditioning
Transient noise pulses at the input data stream are re-
jected by the Noise Rejection Filter. Pulse width rejec-
tion is proportional to transmit data rate.
The Carrier Detection circuitry detects the presence of
an incoming data frame, by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock ac-
quisition. Clock acquisition requires a valid Manchester
bit pattern of 1010b to lock onto the incoming message.
When input amplitude and pulse width conditions are
met at DI , the internal enable signal from the MEN-
DEC to controller (IRXEN) is asserted and a clock ac-
quisition cycle is initiated.
Clock Acquisition
When there is no activity at DI (receiver is idle), the re-
ceive oscillator is phase locked to the internal transmit
clock. The first negative clock transition (bit cell center
of first valid Manchester 0) after IRXEN is asserted in-
terrupts the receive oscillator. The oscillator is then re-
started at the second Manchester 0 (bit time 4) and is
DI
*Internal signal
Figure 35. Receiver Block Diagram
Receiver
Reject
Noise
Filter
Data
Am79C971
phase locked to it. As a result, the MENDEC acquires
the clock from the incoming Manchester bit pattern in 4
bit times with a 1010b Manchester bit pattern.
IRXCLK and IRXDAT are enabled 1/4 bit time after
clock acquisition in bit cell 5. IRXDAT is at a HIGH state
when the receiver is idle (no IRXCLK). IRXDAT, how-
ever, is undefined when clock is acquired and may re-
main HIGH or change to LOW state whenever IRXCLK
is enabled. At 1/4 bit time into bit cell 5, the controller
portion of the Am79C971 controller sees the first IRX-
CLK transition. This also strobes in the incoming fifth bit
to the MENDEC as Manchester 1. IRXDAT may make
a transition after the IRXCLK rising edge in bit cell 5,
but its state is still undefined. The Manchester 1 at bit 5
is clocked to IRXDAT output at 1/4 bit time in bit cell 6.
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection circuit. This circuit ensures that the phase-
locked clock remains locked on the received signal. In-
dividual bit cell phase corrections of the Voltage Con-
trolled Oscillator (VCO) are limited to 10% of the phase
difference between BCC and phase-locked clock.
Hence, input data jitter is reduced in IRXCLK by 10
to 1.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI inputs
after IRXEN is asserted for an end of message. IRXEN
deasserts 1 to 2 bit times after the last positive transi-
tion on the incoming message. This initiates the end of
reception cycle.
Manchester
Decoder
Carrier
Detect
Circuit
IRXDAT*
IRXCLK*
IRXEN*
20550D-38
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