AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 175

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

2-0
BCR28: Expansion Bus Port Address Lower (Used
for Flash/EPROM and SRAM Accesses)
Bit
31-8
15-0
CLK_FAC
000
001
010
011
1XX
CLK_FAC
RES
EPADDRL
Name
Table 39. CLK_FAC Values
Clock Factor
1
1/2 (divide by 2)
Reserved
1/4 (divide by 4)
Reserved
Clock Factor. These bits are used
to select whether the clock select-
ed by EBCS is used directly or if it
is divided down to give a slower
clock for running the Expansion
Bus access cycles. The possible
factors are given in Table 39.
Reserved locations. Written as
zeros and read as undefined.
Expansion Port Address Lower.
This address is used to provide
addresses for the Flash and
SRAM port accesses.
CAUTION: Care should be ex-
ercised when choosing the PCI
clock pin because of the nature
of the PCI clock signal. The PCI
specification states that the
PCI clock can be stopped. If
that can occur while it is being
used for the Expansion Bus
clock data, corruption will re-
sult.
CAUtiON: The external clock
source used to drive the EB-
CLK pin must be a continuous
clock source at all times.
Read accessible always; write
accessible only when the STOP
bit is set. CLK_FAC is set to 000b
during H_RESET and is unaffect-
ed by S_RESET or STOP.
SRAM accesses are started
when a read or write is performed
on BCR30 and the FLASH (BCR
29, bit 15) is set to 0. During
SRAM accesses only bits in the
EPADDRL are valid. Since all
Description
P R E L I M I N A R Y
Am79C971
BCR29: Expansion Port Address Upper (Used for
Flash/EPROM Accesses)
Bit
31-16 RES
15
14
FLASH
LAAINC
Name
SRAM accesses are word orient-
ed only, EPADDRL[0] is the least
significant word address bit. On
any byte write accesses to the
SRAM, the user will have to fol-
low
scheme. On any byte read ac-
cesses to the SRAM, the user will
have to chose which byte is
needed from the complete word
returned in BCR30.
Flash accesses are started when
a read or write is performed on
BCR30 and the FLASH (BCR 29,
bit 15) is set to 1. During Flash
accesses all bits in EPADDR are
valid.
Read accessible always; write
accessible only when the STOP
is set or when SRAM SIZE
(BCR25, bits 7-0) is 0. EPADDRL
is undefined after H_RESET and
is unaffected by S_RESET or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Flash Access. When the FLASH
bit is set to 1 the Expansion Bus
access will be a Flash cycle.
When FLASH is set to 0 the Ex-
pansion Bus access will be a
SRAM cycle. For a complete de-
scription see the section on Ex-
pansion Bus Interface. This bit is
only applicable to reads or writes
to EBDATA (BCR30). It does not
affect Expansion ROM accesses
from the PCI system bus.
Read accessible always; write
accessible only when the STOP
bit is set. FLASH is 0 after
H_RESET and is unaffected by
S_RESET or the STOP bit.
Lower Address Auto Increment.
When the LAAINC bit is set to 1,
the Expansion Port Lower Ad-
dress will automatically increment
by one after a read or write ac-
Description
the
read-modify-write
175