AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 18

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

PIN DESCRIPTIONS
PCI Interface
AD[31:0]
Address and Data
Address and data are multiplexed on the same bus in-
terface pins. During the first clock of a transaction,
AD[31:0] contain a physical address (32 bits). During
the subsequent clocks, AD[31:0] contain data. Byte or-
dering is little endian by default. AD[07:0] are defined
as the least significant byte (LSB) and AD[31:24] are
defined as the most significant byte (MSB). For FIFO
data transfers, the Am79C971 controller can be pro-
grammed for big endian byte ordering. See CSR3, bit 2
(BSWP) for more details.
During the address phase of the transaction, when the
Am79C971 controller is a bus master, AD[31:2] will ad-
d r e s s t h e a c t i ve D o u bl e Wo r d ( DWo r d ) . Th e
Am79C971 controller always drives AD[1:0] to ’00’ dur-
ing the address phase indicating linear burst order.
When the Am79C971 controller is not a bus master, the
AD[31:0] lines are continuously monitored to determine
if an address match exists for slave transfers.
During the data phase of the transaction, AD[31:0] are
driven by the Am79C971 controller when performing
bus master write and slave read operations. Data on
AD[31:0] is latched by the Am79C971 controller when
performing bus master read and slave write operations.
When RST is active, AD[31:0] are inputs for NAND tree
testing.
C/BE[3:0]
Bus Command and Byte Enables
Bus command and byte enables are multiplexed on the
same bus interface pins. During the address phase of
the transaction, C/BE[3:0] define the bus command.
During the data phase, C/BE[3:0] are used as byte en-
ables. The byte enables define which physical byte
lanes carry meaningful data. C/BE0 applies to byte 0
(AD[07:0]) and C/BE3 applies to byte 3 (AD[31:24]).
The function of the byte enables is independent of the
byte ordering mode (BSWP, CSR3, bit 2).
When RST is active, C/BE[3:0] are inputs for NAND
tree testing.
CLK
Clock
This clock is used to drive the system bus interface and
the internal buffer management unit. All bus signals are
sampled on the rising edge of CLK and all parameters
are defined with respect to this edge. The Am79C971
controller normally operates over a frequency range of
10 to 33 MHz on the PCI bus due to networking de-
mands. See the Frequency Demands for Network Op-
18
Input/Output
Input/Output
Input
Am79C971
eration section for details. The Am79C971 controller
will support a clock frequency of 0 MHz after certain
precautions are taken to ensure data integrity. This
clock or a derivation is not used to drive any network
functions.
When RST is active, CLK is an input for NAND tree
testing.
DEVSEL
Device Select
The Am79C971 controller drives DEVSEL when it de-
tects a transaction that selects the device as a target.
The device samples DEVSEL to detect if a target
claims a transaction that the Am79C971 controller has
initiated.
When RST is active, DEVSEL is an input for NAND tree
testing.
FRAME
Cycle Frame
FRAME is driven by the Am79C971 controller when it
is the bus master to indicate the beginning and duration
of a transaction. FRAME is asserted to indicate a bus
transaction is beginning. FRAME is asserted while
data transfers continue. FRAME is deasserted before
the final data phase of a transaction. When the
Am79C971 controller is in slave mode, it samples
FRAME to determine the address phase of a transac-
tion.
When RST is active, FRAME is an input for NAND tree
testing.
GNT
Bus Grant
This signal indicates that the access to the bus has
been granted to the Am79C971 controller.
The Am79C971 controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts GNT
without an active REQ from the Am79C971 controller,
the device will drive the AD[31:0], C/BE[3:0] and PAR
lines.
When RST is active, GNT is an input for NAND tree
testing.
IDSEL
Initialization Device Select
This signal is used as a chip select for the Am79C971
controller during configuration read and write transac-
tions.
When RST is active, IDSEL is an input for NAND tree
testing.
1. Not including test features.
Input/Output
Input/Output
Input
Input