AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 178

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

10-8
7
6
178
110-111 Reserved
APDW
000
001
010
011
100
101
APDW
DANAS
XPHYRST
Continuous (26 s @ 2.5 MHz)
Every 128 MDC cycles (103 s @ 2.5 MHz)
Every 256 MDC cycles (206 s @ 2.5 MHz)
Every 512 MDC cycles (410 s @ 2.5 MHz)
Every 1024 MDC cycles (819 s @ 2.5 MHz)
Every 2048 MDC cycles (1640 s @ 2.5 MHz)
Table 41. APDW Values
MII Auto-Poll Dwell Time. APDW
determines the dwell time be-
tween MII Management Frames
accesses
turned on. See Table 41.
Read/Write accessible always.
APDW is set to 100h after
H_RESET and is unaffected by
S_RESET and the STOP bit.
Disable Auto-Negotiation Auto
Setup. When DANAS is set, the
Am79C971 controller after a
H_RESET or S_RESET will re-
main dormant and not automati-
cally startup the Auto-Negotiation
section or the enhanced automat-
ic port selection section. Instead,
the Am79C971 controller will wait
for the software driver to setup
the Auto-Negotiation portions of
the device. The automatic port
selection for Am79C971 control-
ler will resemble the Pcnet-PCI II
controller. The MII programming
in BCR33 and BCR34 is still valid.
The Am79C971 controller will not
generate
frames unless Auto-Poll is en-
abled.
External PHY Reset. When XPH-
YRST is set, the Am79C971 con-
troller after an H_RESET or
S_RESET will issue an MII man-
Read/Write accessible always.
APEP
H_RESET and is unaffected by
S_RESET and the STOP bit.
Read/write accessible always.
DANAS is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit.
Auto-Poll
is
Dwell Time
when
any
set
to
management
Auto-Poll is
P R E L I M I N A R Y
0
during
Am79C971
5
4
3
2
XPHYANE
XPHYFD
XPHYSP
MII L
agement frames that will reset the
external PHY. This bit is needed
when there is no way to guaran-
tee the state of the external PHY.
This bit must be reprogrammed
after every H_RESET.
Read/Write accessible always.
XPHYRST
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYRST is only valid when the
internal Network Port Manager is
scanning for a network port.
External PHY Auto-Negotiation
Enable. This bit will force the ex-
ternal PHY into enabling Auto-
Negotiation. When set to 0 the
Am79C971 controller will send a
MII management frame disabling
Auto-Negotiation.
Read/Write accessible always.
XPHYANE
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYANE is only valid when the
internal Network Port Manager is
scanning for a network port.
External PHY Full Duplex. When
set, this bit will force the external
PHY into full duplex when Auto-
Negotiation is not enabled.
Read/Write accessible always.
XPHYFD
H_RESET, and is unaffected by
S_RESET and the STOP bit.
XPHYFD is only valid when the
internal Network Port Manager is
scanning for a network port.
External PHY Speed. When set,
this bit will force the external PHY
into 100 Mbps mode when Auto-
Negotiation is not enabled.
Read/Write accessible always.
XPHYSP
H_RESET, and is unaffected by
S_RESET and the STOP bit.
XPHYSP is only valid when the
internal Network Port Manager is
scanning for a network port.
Media Independent Interface for
Micro Linear 6692. When set, this
is
is
is
is
set
set
set
set
to
to
to
to
0
0
0
0
by
by
by
by