AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 24

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

nibble of the frame. TX_EN transitions synchronous to
TX_CLK rising edges.
Note: The TX_EN pin is multiplexed with the TXEN
pin.
When RST is active, TX_EN is an input for NAND tree
testing.
If the MII port is not selected, the TX_EN pin can be left
floating.
TX_ER
Transmit Error
TX_ER is an output that, if asserted while TX_EN is as-
serted, instructs the MII PHY device connected to the
Am79C971 device to transmit a code group error.
TX_ER is unused and is reserved for future use and will
always be driven to a logical zero.
When RST is active, TX_ER is an input for NAND tree
testing.
If the MII port is not selected, the TX_ER pin can be left
floating.
COL
Collision
COL is an input that indicates that a collision has been
detected on the network medium.
Note: The COL pin is multiplexed with the CLSN pin.
When RST is active, COL is an input for NAND tree
testing.
If the MII port is not selected, the COL pin can be left
floating.
CRS
Carrier Sense
CRS is an input that indicates that a non-idle medium,
due either to transmit or receive activity, has been de-
tected.
Note: The CRS pin is multiplexed with the RXEN pin.
When RST is active, CRS is an input for NAND tree
testing.
If the MII port is not selected, the CRS pin can be left
floating.
RX_CLK
Receive Clock
RX_CLK is a clock input that provides the timing refer-
ence for the transfer of the RX_DV, RXD[3:0], and
RX_ER signals into the Am79C971 device. RX_CLK
must provide a nibble rate clock (25% of the network
data rate). Hence, an MII transceiver operating at 10
Mbps must provide an RX_CLK frequency of 2.5 MHz
and an MII transceiver operating at 100 Mbps must pro-
vide an RX_CLK frequency of 25 MHz. When the exter-
24
Output
Input
Input
Input
Am79C971
nal PHY switches the RX_CLK and TX_CLK, it must
provide glitch-free clock pulses.
Note: The RX_CLK pin is multiplexed with the RXCLK
pin.
When RST is active, RX_CLK is an input for NAND tree
testing.
If the MII port is not selected, the RX_CLK pin can be
left floating.
RXD[3:0]
Receive Data
RXD[3:0] is the nibble-wide MII receive data bus. Data
on RXD[3:0] is sampled on every rising edge of
RX_CLK while RX_DV is asserted. RXD[3:0] is ignored
while RX_DV is de-asserted.
When the EADI is enabled (EADISEL, BCR2, bit 3) and
the Receive Frame Tagging is enabled (RXFRTG,
CSR7, bit 14) and the MII is not selected, the RXD[0]
pin becomes a data input pin for the Receive Frame
Tag (RXFRTGD). See the Receive Frame Tagging sec-
tion for details.
Note: The RXD[0] pin is multiplexed with the
RXFRTGD pin.
When RST is active, RXD[3:0] are inputs for NAND tree
testing.
If the MII port is not selected, the RXS[3:0] pin can be
left floating.
RX_DV
Receive Data Valid
RX_DV is an input used to indicate that valid received
data is being presented on the RXD[3:0] pins and
RX_CLK is synchronous to the receive data. In order
for a frame to be fully received by the Am79C971 de-
vice on the MII, RX_DV must be asserted prior to the
RX_CLK rising edge, when the first nibble of the Start
of Frame Delimiter is driven on RXD[3:0], and must re-
main asserted until after the rising edge of RX_CLK,
when the last nibble of the CRC is driven on RXD[3:0].
RX_DV must then be deasserted prior to the RX_CLK
rising edge which follows this final nibble. RX_DV tran-
sitions are synchronous to RX_CLK rising edges.
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is not selected, the RX_DV pin be-
comes a data input enable pin for the Receive Frame
Tag (RXFRTGE). See the Receive Frame Tagging sec-
tion for details.
Note: The RX_DV pin is multiplexed with the
RXFRTGE pin.
When RST is active, RX_DV is an input for NAND tree
testing.
Input
Input