AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 21

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

larity is programmed to active HIGH, the output is a
totem pole driver.
Note: The LED1 pin is multiplexed with the EESK and
SFBD pins.
The LED1 pin is also used during EEPROM Auto-
Detection to determine whether or not an EEPROM is
present at the Am79C971 controller interface. At the
last rising edge of CLK while RST is active LOW, LED1
is sampled to determine the value of the EEDET bit in
BCR19. It is important to maintain adequate hold time
around the rising edge of the CLK at this time to ensure
a correctly sampled value. A sampled HIGH value
means that an EEPROM is present, and EEDET will be
set to 1. A sampled LOW value means that an EE-
PROM is not present, and EEDET will be set to 0. See
the EEPROM Auto-Detection section for more details.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead in
order to resolve the EEDET setting.
When RST is active, LED1 is an input for NAND tree
testing.
WARNING: The input signal level of LED1 must be
insured for correct EEPROM detection before the
deassertion of RST.
LED2
LED2
This output is designed to directly drive an LED. By de-
fault, LED2 indicates correct receive polarity on the
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR6). The LED2
pin polarity is programmable, but by default it is active
LOW. When the LED2 pin polarity is programmed to
active LOW, the output is an open drain driver. When
the LED2 pin polarity is programmed to active HIGH,
the output is a totem pole driver.
Note: The LED2 pin is multiplexed with the SRDCLK
pin and the MIIRXFRTGE pins.
When RST is active, LED2 is an input for NAND tree
testing.
LED3
LED3
This output is designed to directly drive an LED. By de-
fault, LED3 indicates transmit activity on the network.
This pin can also be programmed to indicate other net-
work status (see BCR7). The LED3 pin polarity is pro-
grammable, but by default it is active LOW. When the
LED3 pin polarity is programmed to active LOW, the
output is an open drain driver. When the LED3 pin po-
larity is programmed to active HIGH, the output is a
totem pole driver.
Special attention must be given to the external circuitry
attached to this pin. When this pin is used to drive an
Output
Output
Am79C971
LED while an EEPROM is used in the system, then
buffering is required between the LED3 pin and the
LED circuit. If an LED circuit were directly attached to
this pin, it would create an I
not be met by the serial EEPROM attached to this pin.
If no EEPROM is included in the system design, then
the LED3 signal may be directly connected to an LED
without buffering. For more details regarding LED con-
nection, see the section on LED Support.
Note: The LED3 pin is multiplexed with the EEDO,
SRD, MIIRXFRTGD pins.
When RST is active, LED3 is an input for NAND tree
testing.
SLEEP
Sleep
When SLEEP is asserted, the Am79C971 controller
performs an internal system reset of the H_RESET
type and then proceeds into a power savings mode. All
Am79C971 controller outputs will be placed in their
normal reset condition. All Am79C971 controller inputs
will be ignored except for the SLEEP pin itself. The sys-
tem must refrain from starting the network operations
of the Am79C971 controller for 0.5 seconds following
the deassertion of the SLEEP pin in order to allow in-
ternal analog circuits to stabilize.
For effects with the Magic Packet™ modes, see the
Magic Packet section.
Both CLK and XTAL1 inputs must have valid clock sig-
nals present in order for the SLEEP command to take
effect.
The SLEEP pin should not be asserted during power
supply ramp up. If it is desired that SLEEP be asserted
at power supply ramp up, then the system must delay
the assertion of SLEEP until three clock cycles after the
completion of hardware reset.
WARNING: The SLEEP pin must not be left uncon-
nected. It should be tied to VDD if the power saving
mode is not used.
Note: The SLEEP pin is multiplexed with the EAR pin.
When RST is active, SLEEP is an input for NAND tree
testing.
XTAL1
Crystal Oscillator In
The internal clock generator uses a 20-MHz crystal that
is attached to the pins XTAL1 and XTAL2. The network
data rate is one-half of the crystal frequency. XTAL1
may alternatively be driven using an external 20-MHz
CMOS level clock signal. Refer to the section on Exter-
nal Crystal Characteristics for more details. This clock
is always required whether or not the inter nal
10BASE-T/AUI ports are enabled. If the internal PHY is
OL
requirement that could
Input
Input
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