AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 31

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

The Am79C971 controller will not assert DEVSEL if it
detects an address match, but the PCI command is not
of the correct type. In memory mapped I/O mode, the
Am79C971 controller aliases all accesses to the I/O re-
sources of the command types Memory Read Multiple
and Memory Read Line to the basic Memory Read
command. All accesses of the type Memory Write and
Invalidate are aliased to the basic Memory Write com-
mand. Eight-bit, 16-bit, and 32-bit non-burst transac-
tions are suppor ted. The Am79C971 controller
decodes all 32 address lines to determine which I/O re-
source is accessed.
The typical number of wait states added to a slave I/O
or memory mapped I/O read or write access on the part
of the Am79C971 controller is six to seven clock cycles,
depending upon the relative phases of the internal
Buffer Management Unit clock and the CLK signal,
DEVSEL
FRAME
IDSEL
TRDY
STOP
IRDY
C/BE
PAR
CLK
AD
Figure 1. Slave Configuration Read
1
DEVSEL is sampled
ADDR
1010
2
PAR
3
BE
4
5
DATA
PAR
6
20550D-4
7
Am79C971
since the internal Buffer Management Unit clock is a di-
vide-by-two version of the CLK signal.
The Am79C971 controller does not support burst trans-
fers for access to its I/O resources. When the host
keeps FRAME asserted for a second data phase, the
Am79C971 controller will disconnect the transfer.
The Am79C971 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit
7), which is hardwired to 1. The Am79C971 controller
is capable of detecting an I/O or a memory-mapped
I/O cycle even when its address phase immediately fol-
lows the data phase of a transaction to a different tar-
get, without any idle state in-between. There will be no
contention on the DEVSEL, TRDY, and STOP signals,
since the Am79C971 controller asserts DEVSEL on
the second clock after FRAME is asserted (medium
timing) See Figure 3 and Figure 4.
DEVSEL
FRAME
IDSEL
TRDY
STOP
IRDY
C/BE
PAR
CLK
AD
Figure 2. Slave Configuration Write
1
ADDR
1011
2
PAR
3
4
DATA
BE
5
PAR
6
20550D-5
7
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