AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 156

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

10
9
8
156
DXCVRCTL DXCVR Control. When the AUI
MPSE
FDLSE
interface is the active network
port, DXCVRCTL controls the as-
sertion of the LED1 output. The
polarity of the asserted state is
controlled by the LEDPOL bit
(BCR4, bit 14). The LED1 pin can
be used to control a DC-to-DC
converter in applications that
want to connect a 10BASE2
MAU, as well as a standard DB15
AUI connector to the Am79C971
AUI port. When DXCVRCTL is
set to 1, the LED1 output will be
asserted. This could be used to
enable a DC-to-DC converter for
10BASE2 MAUs (assuming the
enable input of the DC-to-DC
converter is active high and LED-
POL is cleared to 0). When DX-
CVRCTL is cleared to 0, the
LED1 output will be deasserted.
This would power down the DC-
to-DC
10BASE-T interface is the active
network port, the DXCVR output
is always deasserted.
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when Magic Packet
mode is enabled and a Magic
Packet frame is detected on the
network.
Full-Duplex Link Status Enable.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LED-
OUT signal when the Am79C971
controller is functioning in a Link
Pass state and full-duplex opera-
tion
Am79C971 controller is not func-
tioning in a Link Pass state with
Read/Write accessible always.
DXCVRCTL
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
Read/Write accessible always.
MPSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
is
converter.
enabled.
is
cleared
When
When
P R E L I M I N A R Y
the
the
Am79C971
by
7
6
PSE
LNKSE
full-duplex operation being en-
abled, a value of 0 is passed to
the LEDOUT signal.
When the 10BASE-T port is ac-
tive, a value of 1 is passed to the
LEDOUT signal whenever the
Link Test Function (described in
the T-MAU section) detects a
Link Pass state and the FDEN
(BCR9, bit 0) bit is set. When the
AUI port is active, a value of 1 is
passed to the LEDOUT signal
whenever full-duplex operation
on the AUI port is enabled (both
FDEN and AUIFD bits in BCR9
are set to 1).
Read/Write accessible always.
FDLSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Pulse Stretcher Enable. When
this bit is set, the LED illumination
time is extended for each new oc-
currence of the enabled function
for this LED output. A value of 0
disables the pulse stretcher.
Read/Write accessible always.
PSE is set to 1 by H_RESET and
is not affected by S_RESET or
setting the STOP bit.
Link Status Enable. When this bit
is set, a value of 1 will be passed
to the LEDOUT bit in this register
when the T-MAU is in Link Pass
state. When the T-MAU is in Link
Fail state, a value of 0 is passed
to the LEDOUT bit. This bit does
not reflect the link status of the
external PHY.
The function of this bit is masked
if the 10BASE-T port is operating
in full-duplex mode. This allows a
Half-Duplex Link Status LED and
a Full-Duplex Link Status LED at
the same time.
Read/Write accessible always.
LNKSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.