AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 153

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

12
11
10
100E
MIISE
DXCVRCTL DXCVR Control. When the AUI
100 Mbps Enable. When this bit
is set to 1, a value of 1 is passed
to the LEDOUT bit in this register
when the Am79C971 controller is
operating at 100 Mbps mode. The
indication is valid with both the in-
ternal and external PHYs.
Media Independent Interface Se-
lected Enable. Indicates when the
MII interface is selected. This will
be set when either the Manage-
ment Port State Machine is se-
lecting the MII or when ASEL
(BCR2, bit1) is disabled and
PORTSEL (CSR15, bits 8-7) se-
lects the MII. This could control
relays to switch in and out appro-
priate filters or could control an
external PHY when sharing an
RJ45 connector.
interface is the active network
port, DXCVRCTL controls the as-
sertion of the LED0 output. The
polarity of the asserted state is
controlled by the LEDPOL bit
(BCR4, bit 14). The LED0 pin can
be used to control a DC-to-DC
converter in applications that
want to connect a 10BASE2
MAU, as well as a standard DB15
AUI connector to the Am79C971
AUI port. When DXCVRCTL is
set to 1, the LED0 output will be
asserted. This could be used to
enable a DC-to-DC converter for
10BASE2 MAUs (assuming the
enable input of the DC-to-DC
converter is active high and LED-
POL is cleared to 0). When DX-
CVRCTL is cleared to 0, the
LED0 output will be deasserted.
This would power down the DC-
to-DC
10BASE-T interface is the active
Read/Write accessible always.
100E is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Read/Write accessible always.
MIISE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
converter.
When
P R E L I M I N A R Y
the
Am79C971
9
8
MPSE
FDLSE
network port, the DXCVR output
is always deasserted.
Read/Write accessible always.
DXCVRCTL
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when Magic Packet
frame mode is enabled and a
Magic Packet frame is detected
on the network.
Read/Write accessible always.
MPSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Full-Duplex Link Status Enable.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LED-
OUT signal when the Am79C971
controller is functioning in a Link
Pass state and full-duplex opera-
tion
Am79C971 controller is not func-
tioning in a Link Pass state with
full-duplex operation being en-
abled, a value of 0 is passed to
the LEDOUT signal.
When the 10BASE-T port is ac-
tive, a value of 1 is passed to the
LEDOUT signal whenever the
Link Test Function (described in
the T-MAU section) detects a
Link Pass state and the FDEN
(BCR9, bit 0) bit is set. When the
AUI port is active, a value of 1 is
passed to the LEDOUT signal
whenever full-duplex operation
on the AUI port is enabled (both
FDEN and AUIFD bits in BCR9
are set to 1). When the MII port is
active, a value of 1 is passed to
the LEDOUT signal whenever
full-duplex operation on the MII
port is enabled (FDEN bit in
BCR9 is set to 1).
Read/Write accessible always.
FDLSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
is
enabled.
is
cleared
When
153
the
by