AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 121

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

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CSR4: Test and Features Control
Certain bits in CSR4 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR4 and write back
the value just read to clear the interrupt condition.
Bit
31-16
15
RES
RES
Name
RES
EN124
BSWP bit. Descriptor transfers
are not affected by the setting of
the BSWP bit. RDP, RAP, BDP
and PCI configuration space ac-
cesses are not affected by the
setting of the BSWP bit. Address
PROM transfers are not affected
by the setting of the BSWP bit.
Expansion ROM accesses are
not affected by the setting of the
BSWP bit.
Note that the byte ordering of the
PCI bus is defined to be little En-
dian. BSWP should not be set to
1 when the Am79C971 controller
is used in a PCI bus application.
Read/Write accessible always.
BSWP is cleared by H_RESET or
S_RESET and is not affected by
STOP.
value of this bit is a 0. Writing a 1
to this bit has no effect on device
function. If a 1 is written to this bit,
then a 1 will be read back. Exist-
ing drivers may write a 1 to this bit
for compatibility, but new drivers
should write a 0 to this bit and
should treat the read value as un-
defined.
value of this bit is a 0. Writing a 1
to this bit has no effect on device
function. If a 1 is written to this bit,
then a 1 will be read back. Exist-
ing drivers may write a 1 to this bit
for compatibility, but new drivers
should write a 0 to this bit and
should treat the read value as un-
defined.
zeros and read as undefined.
EN124 to 1 allows the user to
Reserved location. The default
Reserved location. The default
Description
Reserved locations. Written as
Enable CSR124 access. Setting
Am79C971
14
13
12
11
APAD_XMT Auto Pad Transmit. When set,
DMAPLUS Writing and reading from this bit
RES
TXDPOLL
Read/Write accessible always.
ENTST is cleared by H_RESET
or S_RESET and is unaffected by
the STOP bit.
Read/Write accessible always.
TXDPOLL
H_RESET or S_RESET and is
unaffected by the STOP bit.
Read/Write accessible always.
APAD_XMT
H_RESET or S_RESET and is
unaffected by the STOP bit.
write to bits in CSR124, which en-
ables
(GPSIEN, bit 4) and Runt Packet
Accept mode (RPA, bit 3). Once
these bits are accessed, EN124
must be cleared back to 0.
has no effect. DMAPLUS is al-
ways set to 1.
Reserved Location. Written as
zero and read as undefined.
ing. If TXDPOLL is set, the Buffer
Management Unit will disable
transmit polling. Likewise, if TXD-
POLL is cleared, automatic trans-
mit
TXDPOLL is set, TDMD bit in
CSR0 must be set in order to ini-
tiate a manual poll of a transmit
descriptor. Transmit descriptor
polling will not take place if TXON
is reset. Transmit polling will take
place following Receive activi-
ties.
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes including FCS.
The FCS is calculated for the en-
tire frame, including pad, and ap-
pended after the pad field.
APAD_XMT will override the pro-
gramming of the DXMTFCS bit
(CSR15, bit 3) and of the
ADD_FCS/NO_FCS bit (TMD1,
bit 29) for frames shorter than 64
bytes.
Transmit Disable Transmit Poll-
polling
the
is
is
GPSI
is
cleared
cleared
enabled.
interface
121
by
by
If