AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 108

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

The following is a list of the registers that would typically
need to be periodically read and perhaps written during
the normal running operation of the Am79C971 control-
ler within a system. Each of these registers contains
control bits, or status bits, or both.
RAP
CSR0
CSR3
CSR4
CSR5
CSR7
CSR112
CSR114
The following registers are only necessary if an exter-
nal PHY device is being used and accessed.
BCR32
BCR33
BCR34
These registers are intended to be used only for testing
and diagnostic purposes. Those registers not included
in any of the above lists can be assumed to be intended
for diagnostic purposes.
PCI Configuration Registers
PCI Vendor ID Register
Offset 00h
The PCI Vendor ID register is a 16-bit register that iden-
tifies the manufacturer of the Am79C971 controller.
AMD’s Vendor ID is 1022h. Note that this vendor ID is
not the same as the Manufacturer ID in CSR88 and
CSR89. The vendor ID is assigned by the PCI Special
Interest Group.
The PCI Vendor ID register is located at offset 00h in
the PCI Configuration Space. It is read only.
PCI Device ID Register
Offset 02h
The PCI Device ID register is a 16-bit register that
uniquely identifies the Am79C971 controller within
AMD's product line. The Am79C971 Device ID is
2000h. Note that this Device ID is not the same as the
Part number in CSR88 and CSR89. The Device ID is
assigned by AMD. The Device ID is the same as the
PCnet-PCI II (Am79C970A) device.
The PCI Device ID register is located at offset 02h in
the PCI Configuration Space. It is read only.
This register is the same as BCR35 and can be written
by the EEPROM.
108
Test Registers
Register Address Port
Am79C971 Controller Status
Interrupt Masks and Deferral Control
Test and Features Control
Extended Control and Interrupt
Extended Control and Interrupt2
Missed Frame Count
PCI Status register
MII Control and Status
MII Address
MII Management Data
Am79C971
PCI Command Register
Offset 04h
The PCI Command register is a 16-bit register used to
control the gross functionality of the Am79C971 con-
troller. It controls the Am79C971 controller's ability to
generate and respond to PCI bus cycles. To logically
disconnect the Am79C971 device from all PCI bus cy-
cles except configuration cycles, a value of 0 should be
written to this register.
The PCI Command register is located at offset 04h in
the PCI Configuration Space. It is read and written by
the host.
Bit
15-10 RES
9
8
7
6
Name
FBTBEN
SERREN
RES
PERREN
Description
ros; write operations have no ef-
fect.
as zero; write operations have no
effect. The Am79C971 controller
will not generate Fast Back-to-
Back cycles.
sertion of the SERR pin. SERR is
disabled
cleared. SERR will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
ros; write operations have no ef-
fect.
Enables the parity error response
functions. When PERREN is 0
and the Am79C971 controller de-
tects a parity error, it only sets the
Detected Parity Error bit in the
PCI Status register. When PER-
REN is 1, the Am79C971 control-
ler
detection of a data parity error. It
also sets the DATAPERR bit (PCI
Status register, bit 8), when the
data parity error occurred during
a master cycle. PERREN also
enables reporting address parity
Reserved locations. Read as ze-
Fast Back-to-Back Enable. Read
SERR Enable. Controls the as-
SERREN
Reserved location. Read as ze-
Parity Error Response Enable.
asserts
when
is
PERR
SERREN
cleared
on
the
by
is