AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 115

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

Control and Status Registers
The CSR space is accessible by performing accesses
to the RDP (Register Data Port). The particular CSR
that is read or written during an RDP access will de-
pend upon the current setting of the RAP. RAP serves
as a pointer into the CSR space.
CSR0: Am79C971 Controller Status and Control
Register
Certain bits in CSR0 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR0 and write back
the value just read to clear the interrupt condition.
Bit
31-16
15
14
Name
RES
ERR
BABL
read access will yield undefined
values.
Read/Write accessible always.
RAP is cleared by H_RESET or
S_RESET and is unaffected by
setting the STOP bit.
zeros and read as undefined.
CERR, MISS, and MERR. ERR
remains set as long as any of the
error flags are true.
Read accessible always. ERR is
read only. Write operations are
ignored.
error. BABL is set by the
Am79C971 controller when the
transmitter has been on the chan-
nel longer than the time required
to send the maximum length
frame. BABL will be set if 1519
bytes or greater are transmitted.
When BABL is set, INTA is as-
serted if IENA is 1 and the mask
bit BABLM (CSR3, bit 14) is 0.
BABL assertion will set the ERR
bit, regardless of the settings of
IENA and BABLM.
Read/Write accessible always.
BABL is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
Description
Reserved locations. Written as
Error is set by the OR of BABL,
Babble is a transmitter time-out
BABL
is
cleared
Am79C971
by
13
12
CERR
MISS
H_RESET, S_RESET, or by set-
ting the STOP bit.
When the 10BASE-T port is se-
lected, for both half-duplex and
full-duplex operation, CERR will
be set after a transmission if the
T-MAU is in Link Fail state.
When the MII port is selected,
CERR is only reported when the
external PHY is operating as a
10BASE-T PHY and if the exter-
nal T-MAU is in Link Fail state.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
Read/Write accessible always.
CERR is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
When MISS is set, INTA is as-
serted if IENA is 1 and the mask
bit MISSM (CSR3, bit 12) is 0.
MISS assertion will set the ERR
Am79C971 controller when the
device operates in half-duplex
mode and the collision inputs to
the AUI or to the GPSI port failed
to activate within 20 network bit
times after the chip terminated
transmission (SQE Test). This
feature is a transceiver test fea-
ture. CERR reporting is disabled
when the AUI or the GPSI port is
active and the Am79C971 con-
troller operates in full-duplex
mode.
Am79C971 controller when it has
lost an incoming receive frame
resulting from a Receive Descrip-
tor not being available. This bit is
the only immediate indication that
receive data has been lost since
there is no current receive de-
scriptor.
Counter (CSR112) also incre-
ments each time a receive frame
is missed.
Collision Error is set by the
Missed Frame is set by the
CERR
The
is
Missed
cleared
Frame
115
by