AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 182

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

LADRF
The Logical Address Filter (LADRF) is a 64-bit mask
that is used to accept incoming Logical Addresses. If
the first bit in the incoming address (as transmitted on
the wire) is a 1, it indicates a logical address. If the first
PADR
This 48-bit value represents the unique node address
assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and
used for internal address comparison. PADR[0] is com-
pared with the first bit in the destination address of the
incoming frame. It must be 0 since only the destination
address of a unicast frames is compared to PADR. The
six hex-digit nomenclature used by the ISO 8802-3
182
Table 45. R/TLEN Decoding (SSIZE32 = 1)
R/TLEN
11XX
1X1X
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
47
Match = 1 Packet Accepted
Match = 0 Packet Rejected
Received Message
Destination Address
Number of DREs
1
0
1
128
256
512
512
512
16
32
64
Figure 57. Address Match Logic
1
2
4
8
P R E L I M I N A R Y
GEN
CRC
SEL
Am79C971
bit is a 0, it is a physical address and is compared
against the physical address that was loaded through
the initialization block.
A logical address is passed through the CRC genera-
tor, producing a 32-bit result. The high order 6 bits of
the CRC is used to select one of the 64 bit positions in
the Logical Address Filter. If the selected filter bit is set,
the address is accepted and the frame is placed into
memory.
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message
may be intended for the node. It is the node’s responsi-
bility to determine if the message is actually intended
for the node by comparing the destination address of
the stored message with a list of acceptable logical ad-
dresses.
If the Logical Address Filter is loaded with all zeros and
promiscuous mode is disabled, all incoming logical ad-
dresses except broadcast will be rejected. See Figure
57.
(IEEE/ANSI 802.3) maps to the Am79C971 PADR reg-
ister as follows: the first byte is compared with
PADR[7:0], with PADR[0] being the least significant bit
of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3)
byte is compared with PADR[15:8], again from the least
significant bit to the most significant bit, and so on. The
sixth byte is compared with PADR[47:40], the least sig-
nificant bit being PADR[40].
31
32-Bit Resultant CRC
26
64
6
63
MUX
Address Filter
(LADRF)
Logical
0
0
Match
20550D-60