AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 262

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

External SRAM Configuration
F
FIFO DMA Transfers
Framing
Frequency Demands for Network Operation
Full-Duplex
Functions
G
General Description
General Purpose Serial Interface
I
I/O Resources
IEEE 1149.1 (1990) Test Access Port
Interface
Initialization
Initialization Block
Input Signal Conditioning, MENDEC
Instruction Register and Decoding Logic
J
Jabber Function, Twisted Pair Transceiver
L
LADRF
LAPP Flow, Outline of
LAPP Setup
Late Collision
LED Support
Link Test Function, Twisted Pair Transceiver
Look-Ahead Packet Processing (LAPP) Concept D-1
Loopback Features
I-4
Transmit and Receive Message Data
Expansion Bus Interface
Link Status LED Support
Operation
Basic
Detailed
Boundary Scan Register
Instruction Register and Decoding Logic
Other Data Registers
Supported Instructions
TAP Finite State Machine
Buffer Management Unit
Description
DMA Transfers
LADRF
Mode
PADR
RDRA and TDRA
RLEN and TLEN
Encapsulation
103
100
180
182
183
182
181
181
182
D-1
D-1
90
50
60
94
76
75
29
30
75
99
99
99
99
53
47
71
99
74
65
97
73
2
Loss of Carrier
Low Latency Receive Configuration
M
MAC
Magic Packet Mode, Power Saving
Manchester Encoder/Decoder
Manufacturer Contact Information
Master Abort
Master Bus Interface Unit
Master Initiated Termination
Media Access Control
Media Independent Interface
Media Independent Interface
Miscellaneous
Carrier Tracking and End of Message
Clock Acquisition
Data Decoding
External Clock Drive Characteristics
External Crystal Characteristics
Input Signal Conditioning
Jitter Tolerance Definition
MENDEC Transmit Path
PLL Tracking
Receiver Path
Transmitter Timing and Operation
Bus Acquisition
Bus Master DMA Transfers
Collision Handling
Destination Address Handling
Error Detection
Framing
Management
Medium Allocation
Transmit and Receive Message Data
Auto-Poll External PHY Status Polling
Described
Loopback Features
Medium Allocation
MII Management Frames
Basic Burst Read Transfer
Basic Burst Write Transfer
Basic Non-Burst Write Transfer
Burst FIFO DMA Transfers
Descriptor DMA Transfers
Disconnect With Data Transfer
Disconnect Without Data Transfer
FIFO DMA Transfers
Initialization Block DMA Transfers
Master Abort
Master Initiated Termination
Non-Burst FIFO DMA Transfers
Parity Error Response
Preemption During Burst Transaction
Preemption During Non-Burst
Encapsulation
Transaction
60, 61, 62
97, 98
A-2
65
92
72
37
39
39
52
47
40
41
50
47
43
42
50
43
42
42
63
61
61
78
76
69
69
70
71
71
70
70
71
72
70
71
71
70
43
36
36
37
42
60
61
60
62
60
69
62
78