AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 42

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

RTABORT (PCI Status register, bit 12) will be set to
indicate that the Am79C971 controller has received a
target abort. In addition, SINT (CSR5, bit 11) will be set
to 1. When SINT is set, INTA is asserted if the enable
bit SINTE (CSR5, bit 10) is set to 1. This mechanism
can be used to inform the driver of the system error. The
host can read the PCI Status register to determine the
exact cause of the interrupt.
Master Initiated Termination
There are three scenarios besides normal completion
of a transaction where the Am79C971 controller will
terminate the cycles it produces on the PCI bus.
Preemption During Non-Burst Transaction
When the Am79C971 controller performs multiple non-
burst transactions, it keeps REQ asserted until the as-
sertion of FRAME for the last transaction. When GNT
is removed, the Am79C971 controller will finish the cur-
rent transaction and then release the bus. If it is not the
42
DEVSEL
FRAME
TRDY
STOP
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
DEVSEL is sampled
1
Figure 17. Disconnect Without Data Transfer
2
ADDR i
0111
3
PAR
4
DATA
0000
Am79C971
5
PAR
last transaction, REQ will remain asserted to regain
bus ownership as soon as possible. See Figure 19.
Preemption During Burst Transaction
When the Am79C971 controller operates in burst
mode, it only performs a single transaction per bus
mastership period, where transaction is defined as one
address phase and one or multiple data phases. The
central arbiter can remove GNT at any time during the
transaction. The Am79C971 controller will ignore the
deassertion of GNT and continue with data transfers,
as long as the PCI Latency Timer is not expired. When
the Latency Timer is 0 and GNT is deasserted, the
Am79C971 controller will finish the current data phase,
deassert FRAME, finish the last data phase, and re-
lease the bus. If EXTREQ (BCR18, bit 8) is cleared to
0, it will immediately assert REQ to regain bus owner-
ship as soon as possible. If EXTREQ is set to 1, REQ
will stay asserted.
6
7
8
9
10
ADDR i
0111
11
20550D-20