AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 184

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

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ERR
FRAM
OFLO
CRC
BUFF
ERR is the OR of FRAM, OFLO,
CRC, BUFF, or BPE. ERR is set
by the Am79C971 controller and
cleared by the host.
Framing error indicates that the
incoming frame contains a non-
integer multiple of eight bits and
there was an FCS error. If there
was no FCS error on the incom-
ing frame, then FRAM will not be
set even if there was a non-
integer multiple of eight bits in the
frame. FRAM is not valid in inter-
nal loopback mode. FRAM is val-
id only when ENP is set and
OFLO is not. FRAM is set by the
Am79C971
cleared by the host.
Overflow error indicates that the
receiver has lost all or part of the
incoming frame, due to an inabili-
ty to move data from the receive
FIFO into a memory buffer before
the internal FIFO overflowed.
OFLO is set by the Am79C971
controller and cleared by the
host.
CRC indicates that the receiver
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is set by the
Am79C971
cleared by the host. CRC will also
be set when Am79C971 receives
an RX_ER indication from the ex-
ternal PHY through the MII.
Buffer error is set any time the
Am79C971 controller does not
own the next buffer while data
chaining a received frame. This
can occur in either of two ways:
Once the Am79C971 controller or
host has relinquished ownership
of a buffer, it must not change any
field in the descriptor entry.
1. The OWN bit of the next buffer
2. FIFO overflow occurred before
is 0.
the Am79C971 controller was
able to read the OWN bit of
the next descriptor.
controller
controller
P R E L I M I N A R Y
and
and
Am79C971
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STP
ENP
BPE
PAM
If a Buffer Error occurs, an Over-
flow Error may also occur inter-
nally in the FIFO, but will not be
reported in the descriptor status
entry unless both BUFF and
OFLO errors occur at the same
time.
Am79C971
cleared by the host.
Start of Packet indicates that this
is the first buffer used by the
Am79C971 controller for this
frame. If STP and ENP are both
set to 1, the frame fits into a single
buffer. Otherwise, the frame is
spread over more than one buff-
er. When LAPPEN (CSR3, bit 5)
is cleared to 0, STP is set by the
Am79C971
cleared by the host. When LAP-
PEN is set to 1, STP must be set
by the host.
End of Packet indicates that this
is the last buffer used by the
Am79C971 controller for this
frame. It is used for data chaining
buffers. If both STP and ENP are
set, the frame fits into one buffer
and there is no data chaining.
ENP is set by the Am79C971
controller and cleared by the
host.
Bus Parity Error is set by the
Am79C971 controller when a par-
ity error occurred on the bus inter-
face during data transfers to a
receive buffer. BPE is valid only
when ENP, OFLO, or BUFF are
set. The Am79C971 controller will
only set BPE when the advanced
parity error handling is enabled
by setting APERREN (BCR20, bit
10) to 1. BPE is set by the
Am79C971
cleared by the host.
This bit does not exist when the
Am79C971 controller is pro-
grammed to use 16-bit software
structures for the descriptor ring
entries (BCR20, bits 7-0, SW-
STYLE is cleared to 0).
Physical Address Match is set by
the Am79C971 controller when it
accepts the received frame due
BUFF
is
controller
controller
controller
set
by
and
and
and
the